KR920015858A - Multi screen playback circuit and scheme - Google Patents

Multi screen playback circuit and scheme Download PDF

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Publication number
KR920015858A
KR920015858A KR1019910001297A KR910001297A KR920015858A KR 920015858 A KR920015858 A KR 920015858A KR 1019910001297 A KR1019910001297 A KR 1019910001297A KR 910001297 A KR910001297 A KR 910001297A KR 920015858 A KR920015858 A KR 920015858A
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KR
South Korea
Prior art keywords
screen
display
address
memory
screens
Prior art date
Application number
KR1019910001297A
Other languages
Korean (ko)
Other versions
KR930006184B1 (en
Inventor
이영만
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019910001297A priority Critical patent/KR930006184B1/en
Priority to JP04009232A priority patent/JP3107887B2/en
Publication of KR920015858A publication Critical patent/KR920015858A/en
Application granted granted Critical
Publication of KR930006184B1 publication Critical patent/KR930006184B1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2624Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/04Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1737Controllable logic circuits using multiplexers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2101/00Still video cameras

Abstract

내용 없음No content

Description

다중 화면 재생 회로 및 방식Multi screen playback circuit and scheme

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 전자 스틸 비디오 카메라의 블럭도. 제3도는 본 발명의 일실시예의 블럭도. 제4도는 제3도중 다중화된 디스플레이 어드레스 카운터의 구체적인 블럭도.2 is a block diagram of an electronic still video camera according to the present invention. 3 is a block diagram of one embodiment of the present invention. 4 is a detailed block diagram of a multiplexed display address counter of FIG.

Claims (4)

촬상된 비디오 신호를 디지탈화 하여 메모리에 저장하였다가 재생수단을 통해 디스플레이 하는 전자 스틸 비디오 카메라장치에 있어서, 디스플레이 하기를 원하는 화면을 임의로 선택할 수 있는 화면선택 수단과, 상기 화면선택 수단의 화면선택 상태를 감지하여 상기 메모리도 해당 화면을 지정하는 어드레스를 발생하는 마이컴과, 상기 마이컴의 제어를 받아 화면선택 상태에 따라 1화면 혹은 소정 갯수의 화면들에 대한 독출 어드레스를 발생하는 디스플레이 제어수단으로 구성됨을특징으로 하는 다중 디스플레이 재생회로.An electronic still video camera apparatus which digitalizes a captured video signal, stores it in a memory, and displays the same through a playback means, comprising: screen selection means for arbitrarily selecting a screen to be displayed and a screen selection state of the screen selection means; The microcomputer is configured to detect and generate an address for designating a corresponding screen, and display control means for generating a read address for one screen or a predetermined number of screens according to a screen selection state under the control of the microcomputer. Multiple display reproduction circuit. 제1항에 있어서, 디스플레이 제어수단이 한 화면에 저장된 전 화상데이타에 대한 독출 어드레스를 발생하는 1프레임 디스플레이 어드레스 카운터(9)와, 한 화면내의 화상데이타 독출 어드레스를 디스플레이 화면수(n)에 따라 0부터 n씩 증가시켜 가면서 카운트하는 다중 디스플레이 어드레스 카운터(10)와, 마이컴의 제어를 받아 상기 1프레임 디스플레이 어드레스카운터(9) 혹은 다중 디스플레이 어드레스 카운터(10) 출력을 선택적으로 상기 메모리에 공급하는 멀티플렉서(11)로 구성됨을 특징으로 하는 다중화면 재생회로.The display apparatus according to claim 1, wherein the display control means generates a one-frame display address counter 9 for generating a read address for all image data stored in one screen, and an image data read address in one screen according to the display screen number n. A multiple display address counter 10 for counting in increments from 0 to n, and a multiplexer for selectively supplying the output of the one-frame display address counter 9 or the multiple display address counter 10 to the memory under the control of a microcomputer; And a multi-screen playback circuit, characterized in that (11). 제2항에 있어서, 다중 디스플레이 어드레스 카운터(10)가 2화면, 3화면,…,n화면 각각에 대한 디스플레이 어드레스 카운터와 상기 마이컴의 제어를 받아 상기 디스플레이 어드레스 카운터들의 출력중 하나를 선택적으로 출력하는 제2멀틱플렉서(16)로 구성됨을 특징으로 하는 다중 디스플레이 재생회로.3. The multi-display address counter 10 according to claim 2 comprises two screens, three screens,... and a second multiplexer (16) for selectively outputting one of an output of the display address counters under the control of the microcomputer and a display address counter for each of the n screens. 마이컴을 구비하고 촬상된 비디오 신호를 디지탈화하여 메모리에 저장하였다가 재생수단을 통해 디스플레이하는 전자 스틸 비디오 카메라 장치의 화면재생 방식에 있어서, 상기 메모리내에 저장된 다수의 화면 데이타중 임의의 한 화면을 선택할시 선택된 한 화면에 해당하는 1프레임분의 전체 화상데이타 독출 어드레스를 발생하여 상기 메모리의 독출 어드레스로제공하며 상기 메모리내 저장된 다수의 화면데이타중 몇개의 화면들을 임의로 선택할시 한 화면내의 화상에이타 독출 어드레스를 디스플레이 화면수(n)에 따라 0부터 n씩 증가시켜 가면서 카운트 함과 동시에 상기 마이컴에서 선택된 화면을각각 저장하는 어드레스를 발생하여 상기 메모리의 독출 어드레스로 제공하여 수직동기 신호를 소정 분주한 프레임 펄스의 1주기 마다 상기 메모리에 저장된 다수의 화면을 하나씩 순차적으로 디스플레이 하거나 소정 갯수씩 임의로 선택된 화면들을 상기 프레임 펄스의 1주기마다 동시에 디스플레이 함을 특징으로 하는 다중화면 재생방식.A screen reproducing method of an electronic still video camera apparatus having a microcomputer and digitally storing the captured video signal in a memory and displaying the same through a reproducing means, wherein an arbitrary screen is selected from among a plurality of screen data stored in the memory. Generates an entire image data read address for one frame corresponding to a selected screen and provides it as a read address of the memory. When randomly selecting several screens among a plurality of screen data stored in the memory, the image address read address in one screen is selected. According to the number of display screens (n), the counting is incremented from 0 to n, and at the same time, an address for storing the screen selected by the microcomputer is generated and provided to the read address of the memory, thereby providing a vertical sync signal for the predetermined pulse of the frame pulse. The memory every 1 cycle Multiscreen reproduction method of the plurality of screens are stored, characterized in that one at the same time or sequentially display the display every one period of the frame pulse by a predetermined number of randomly selected screen as. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001297A 1991-01-25 1991-01-25 Multi-scene regenerating circuit and method KR930006184B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910001297A KR930006184B1 (en) 1991-01-25 1991-01-25 Multi-scene regenerating circuit and method
JP04009232A JP3107887B2 (en) 1991-01-25 1992-01-22 Multi-screen control circuit and method for electronic still camera

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001297A KR930006184B1 (en) 1991-01-25 1991-01-25 Multi-scene regenerating circuit and method

Publications (2)

Publication Number Publication Date
KR920015858A true KR920015858A (en) 1992-08-27
KR930006184B1 KR930006184B1 (en) 1993-07-08

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Application Number Title Priority Date Filing Date
KR1019910001297A KR930006184B1 (en) 1991-01-25 1991-01-25 Multi-scene regenerating circuit and method

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JP (1) JP3107887B2 (en)
KR (1) KR930006184B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990011622A (en) * 1997-07-24 1999-02-18 윤종용 How to Display Image Data from a Digital Still Camera

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103459859A (en) 2010-12-22 2013-12-18 艾科安特公司 Hydraulic cylinder position sensing and locking system and corresponding method
AU2015318578B2 (en) * 2014-09-17 2020-07-02 Enerpac Tool Group Corp. Portable self-locking lift system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990011622A (en) * 1997-07-24 1999-02-18 윤종용 How to Display Image Data from a Digital Still Camera

Also Published As

Publication number Publication date
JP3107887B2 (en) 2000-11-13
KR930006184B1 (en) 1993-07-08
JPH0537891A (en) 1993-02-12

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