JP3107887B2 - Multi-screen control circuit and method for electronic still camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit and a method for reading out image data recorded in a main memory and displaying it on an image display unit in an electronic still camera.
In particular, the present invention relates to a multi-screen control circuit for displaying a plurality of images recorded in a main memory one by one through an image display unit or displaying a plurality of images at the same time and searching the same, and a method therefor.

[0002]

2. Description of the Related Art Generally, in electronic still cameras, C
An image signal photoelectrically converted by a photoelectric conversion element such as a CD is converted into digital image data by an analog / digital converter and recorded on a recording medium in frame units. The image data recorded on the recording medium can be erased for subsequent recording or recorded and stored on another recording medium. At this time, the former is a buffer memory and the latter is a main memory. Usually, the storage capacity of the main memory is set larger than the storage capacity of the buffer memory so that a large number of image data can be recorded / stored. A plurality of image data recorded in the main memory are processed by data processing means such as a microcomputer and can be provided for other purposes of the user, for example, copying, transmission, reproduction and the like. To check the contents of the image data recorded in the main memory, the image data recorded in the main memory is copied to another buffer memory (reproduction is used as a buffer memory), and the data in the reproduction buffer memory is sequentially copied. After reading the data and converting it into an analog signal through a digital / analog converter, the composite resolution signal is formed and displayed on a display device such as a monitor attached to the electronic still camera.

FIG. 1 shows a recording screen display circuit of a conventional electronic camera. An image signal generated by a video input unit 1 having a photoelectric conversion element such as a CCD is converted into digital image data via an analog / digital converter 2 and recorded in a buffer memory 3 in frame units. Buffer memory 3
The image data recorded in the main memory 4 can be erased for subsequent recording or recorded and stored in the main memory 4. The main memory 4 is capable of recording a plurality of image data, and restricts and records one image data to an area called a page (PAGE) in order to efficiently manage the recorded image data. The recording area of one page is the same as or larger than the recording area required for recording one image data, and different pages mean that different image data are recorded. That is, it is possible to manage the image data in units of pages irrespective of the content of the image data recorded by the microcomputer. FIG. 2 shows an address designation relationship for the image data in the main memory 4 of FIG. Here, it is assumed that the size of one frame is 256 bytes × 256 bytes and the number of pages is 16 pages. Since the image data in a given page is specified by being divided into a horizontal component and a vertical component, the horizontal component corresponds to the horizontal address of the image data, and the vertical component corresponds to the vertical address of the image data. Would be equivalent. When trying to increase the resolution of the display screen or use the capacity of one field in the non-sequential scanning method, 512
Bytes × 512 bytes can also be used. In this case, if the main memory has the same storage capacity, four pages are used. The image data recorded in each area of the main memory 4 can be read out and confirmed through the image display unit 7, and can be erased or moved to another area in the main memory 4 to record another image. It is. The control of the main memory 4 is performed by the microcomputer 9. In order to check the recorded image data through the image display unit 7, one of various pages in the main memory 4 is selected, and the image data in the page is read out and recorded in the buffer memory 5 for reproduction.
The image data recorded in the reproduction buffer memory 5 is read out according to a horizontal and vertical cycle suitable for display on the image display unit 7 and is converted into analog data by the digital / analog converter 6. The video signal converted to analog data is displayed through the image display unit 7. In this case, the image data recorded in the main memory 4 is read page by page and recorded in the reproduction memory 5, so that the user repeats the above operation as much as necessary to confirm a large number of images. There was the inconvenience of having to specify the area.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus capable of designating one or a plurality of image data recorded in a main memory and simultaneously displaying the designated image data on an image display unit. is there.

Another object of the present invention is to provide a method capable of designating one or a plurality of image data recorded in a main memory and simultaneously displaying the designated image data on a screen display unit.

[0006]

In order to achieve the above object, an apparatus according to the present invention comprises a screen selecting means capable of receiving a user's selection request, and an image display by interpreting a screen selection inputted through the screen selecting means. A microcomputer for performing a control operation for displaying one or a plurality of frames of image data through the unit, and a multiplex screen control means for implementing the respective screen states under the control of the microcomputer. I do.

In the control of such a multi-screen reproduction circuit, if a search mode is not specified, a general operation mode is operated. If a search mode is specified, output from the reproduction buffer memory to the image display unit is prohibited. A reproducing process of controlling the multiplexed screen control unit by the microcomputer in accordance with a command from the screen selecting unit to read out the image data of the main memory and recording the image data in the reproducing buffer memory; and a reproducing buffer after the recording process is completed. An output step of restarting the output from the memory to the image display unit, a standby step of performing the output step and waiting for a command of the screen selection unit, and a screen currently displayed if an end signal is received in the standby step. And returning to the normal mode by reproducing the screen displayed before performing the search process.

[0008]

Therefore, according to the present invention, a plurality of screens can be displayed on the screen display unit, and the time for searching for a plurality of image data recorded in the main memory of the electronic still camera can be saved.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 3, a multi-screen display circuit according to the present invention includes a video input unit 1 for generating an analog video signal from an object to be imaged, and an A / D converter for converting the analog video signal into digital video data. Device 2, a buffer memory 3 for recording the digital video data in units of one frame, a main memory 4 for recording / archiving image data in the buffer memory 3, and an image read from the main memory 4. A reproduction buffer memory 5 capable of storing data in frame units; a D / A converter 6 for converting digital video data read from the reproduction buffer memory 5 into an analog video signal; An image display section 7 to be displayed on the top and a screen selection for selecting a screen to be displayed on the image display section 7 by the user 8, a microcomputer 9 for interpreting a screen selection request input through the screen selection unit 8 to perform a predetermined control operation, and a read address for generating respective screen states under the control of the microcomputer 9 Is provided. The screen selection unit 8 is for inputting a user's command regarding the search mode operation, and includes means for specifying a search mode and means for specifying a page of a screen to be reproduced. Microcomputer 9
Designates a page address of image data recorded in the main memory 4 for performing a control operation for providing a reproduction screen in the reproduction buffer memory 5 in response to a command from the screen selection unit 8, and 10 are controlled. The multi-screen control unit 10 includes a multiplexer, a plurality of address generators, a horizontal / vertical counter, and a flip-flop for generating a read address in a page specified by the microcomputer 9 under the control of the microcomputer 9.

FIG. 4 is a block diagram of the multiplexed image control unit 10 according to the present invention, in which a plurality of N-screen address generation units 141, 142, 143, and 14 for generating multiplexed-screen display addresses are provided.
,..., 14N and the multiplexer 1 for selectively outputting the output of the N-screen address generator and applying the output to the main memory 4.
3, a horizontal / vertical counter 12 for generating horizontal and vertical addresses of the reproduction buffer memory 5, a horizontal / vertical overflow detector 15 for detecting an overflow of the horizontal / vertical counter 12, and a flip-flop 11 for controlling a clock input to the horizontal / vertical counter. It is comprised including.
Here, the horizontal / vertical counter 12 is a buffer memory 5 for reproduction.
And an operation of controlling the addressing process of the reproduction buffer memory 5 so as to be synchronized with the addressing of the main memory 4 for the image data.

FIG. 5 shows an example of the N-screen address generator. Each of the N screen address generators 141, 142,
143, 144,..., 14N are horizontal address generators 14N so that they can be counted at predetermined intervals in the horizontal and vertical directions.
H and vertical address generator 14NV and OR gate 14N
It is composed of O. The horizontal address generator 14NH is connected to a first counter 14NH-2 for providing an even multiple of the input clock signal, a second counter 14NH-3 for providing an integer multiple of the input clock signal, and a second counter connected to the first counter. The output values of the first adder 14NH-4 and the first adder 14NH-4, which add the output value of the 1 multiplier 14NH-1, the output value of the first counter 14NH-2, and the output value of the second counter 14NH-3, A horizontal overflow detector 14NH-5 for monitoring and detecting whether or not overflow has occurred is provided.

The vertical address generator 14NV has a third counter 14NV-2 for providing an even multiple of the input clock signal and a fourth counter 1N for providing an integer multiple of the input clock signal.
4 NV-3 and a second multiplier 14 connected to the third counter
The output values of the second adder 14NV-4 and the second adder 14NV-4, which add the output value of the NV-1 and the third counter 14NV-2 and the output value of the fourth counter 14NV-3, are monitored. A vertical overflow detector 14NV-5 for detecting whether or not overflow has occurred is provided.

The OR gate 14NO performs a logical sum operation between the output of the horizontal overflow detector 14NH-5 and the output of the vertical overflow detector 14NV-5.

On the other hand, in displaying a plurality of images on the image display section 7, it is necessary to express the image data in the main memory 4 by compressing it. In the present invention, as a method of compressing image data, a method of skipping and reading image data recorded in the main memory 4 in a horizontal or vertical direction by a predetermined interval determined by the number of screens is used. A generator should be provided. Further, in order to provide a plurality of divided screens in the horizontal or vertical direction, each of the horizontal and vertical address generators performs a count of an integral multiple (1, 2, 3,..., N) of the input clock. Should. The present invention includes a counter that counts an even multiple of an input clock and a counter that counts an integer multiple. By adding the output values of the counter that counts an even multiple and the counter that counts an integer multiple, the count value of a certain multiple can be received. The method of counting an even-numbered value is achieved by multiplying an input clock using an even-numbered multiplier and supplying the multiplied clock to a counter.

The operation of reading from the main memory 4 in the case of searching for the four image data shown in FIG. First, the first horizontal line of the first image data is skipped every other pixel by the image data compression method and read out in the horizontal direction. After the first horizontal line of the first image data is read out, the second horizontal line is completed. Reading out the first horizontal line of the image data is performed in the same manner. The read image data of the horizontal line is recorded on the horizontal line of the first frame of the reproduction buffer memory. When the recording on the first horizontal line of the reproduction buffer memory 5 is completed, the vertical address of the reproduction buffer memory 5 is increased by one. The horizontal lines of the first and second image data on the main memory 4 are skipped by one line in the vertical direction, and the read operation for the third horizontal line of the first and second image data is performed in the same manner as described above. . Whenever the image data to be read from the main memory 4 changes, the microcomputer 9 needs to sense that the reading of each image data in the horizontal and vertical directions is completed in order to designate each page address. The completion of the reading of the horizontal or vertical components of the image data is monitored by monitoring the respective address values applied to the address bus of the main memory 4 from the horizontal address generator 144H or the vertical address generator 144V of the four-screen address generator 144. And the most significant bit (M
If the falling edge of SB) is detected, it is possible to determine whether the reading of the horizontal or vertical line is completed. The overflow detecting operation is performed by the horizontal overflow detecting unit 144.
This is performed by the H-5 or vertical overflow detector 144V-5. The detected overflow signal is sensed by the microcomputer 9, and after sensing the overflow signal, the microcomputer 9 applies the page address of the image data to be read next to the address bus of the main memory 4. On the other hand, the overflow signal is supplied to the D flip-flop 11 connected to the input of the horizontal / vertical counter through the OR gate 144O so that the horizontal / vertical counter 12 of the reproduction buffer memory 5 stops while the microcomputer 9 applies the page address.
Is input by the disable signal. After applying the page address of the second screen to the address bus of the main memory 4, the microcomputer 9 issues a start signal to clear the D flip-flops of the overflow detectors 144H-5 and 144V-5. On the other hand, the start signal from the microcomputer 9 is D
The flip-flop 11 is also cleared and the horizontal / vertical counter 1 is cleared.
The D flip-flop 1 which has inhibited the clock input to the clock 2 is enabled, the clock is supplied again, and the operation of the horizontal / vertical counter 12 is restarted. At the same time, the horizontal and vertical address generators 144H of the screen 4 address generator 144,
The 144 V operation is resumed. On the other hand, if the vertical overflow signal is generated, it means that the reading of the image data in the designated page area has been completed. Therefore, the microcomputer 9 applies the page address of the next image data. Is the same as Horizontal / vertical counter 1
The overflow signal generated by the overflow detection unit 15 connected to the most significant bit (MSB) of the address signal output in Step 2 is used as an end signal to terminate the operation of the 4-screen address generation unit and end the recording in the reproduction buffer memory 5. It is supplied to the microcomputer 9 as a signal indicating that the operation has been performed.

FIG. 6 shows an example of a flowchart of the present invention. If the search mode is designated by the screen selection unit 8 while operating in the normal mode, the search mode is performed. First, it is checked whether the command of the screen selection unit 8 is a command for designating the end of the search (step 600). If not, it is checked whether the screen creation operation has been performed in the previous search mode (step 610). If the image data specified by the previous search command is being recorded in the reproduction buffer memory by the multiplex screen control routine, it is necessary to stop this and record the newly specified multiplex screen (step 620). The signal applied from the screen selection unit 8 to the microcomputer 9 in the search mode is a signal indicating the page number to be displayed or the end of the search mode. The microcomputer 9 changes the page number to be displayed to a corresponding page address and stores it (6).
30 stages). When the page address of the image data to be displayed is prepared, the output to the image display unit 7 is stopped (step 670). Perform a multiple screen control routine. The display screen is recorded in the reproduction buffer memory by controlling the multiplex screen control unit 10 (step 680). Image display section 7
Then, the image recorded in the reproduction buffer memory is displayed on the image display unit 7 (step 690). On the other hand, if it is a command for designating the end of the search, it is checked by the multiplexed screen controller 10 whether or not recording to the reproduction buffer memory has been performed (step 640). If recording in the reproduction buffer memory has been performed by the multiplex screen control unit 10 in step 640, this is stopped (step 650) to display the screen displayed before the reproduction screen. A page address is provided (step 660), and the same reproduction operation is performed (steps 670-690).

FIG. 7 shows an example of the search screen display routine in FIG. The number of images to be displayed is determined, and the process branches to a corresponding N-screen control routine (steps 700-790).

FIG. 8 shows an example of the one-screen display routine of FIG. First, an operation display flag for indicating that the reproduction buffer memory is recording is set by the multiplex screen control unit (step 800). The operation display flag is used when the microcomputer 9 checks whether or not the multi-screen control unit 10 operates. The page address of the designated image data is applied to the address bus of the main memory 4 (step 810). The horizontal / vertical counter 12 is reset to initialize the operation of the horizontal / vertical counter 12 (step 820). The horizontal / vertical counter 12 is operated to start reading from the main memory 4 and recording to the reproduction buffer memory 5 (step 830).
The end signal from the horizontal stage counter 12 is checked, and the process waits for the completion of the recording (step 840). When the recording operation is completed, the operation display flag is reset, and the one-screen control routine is ended (steps 850-860).

FIG. 9 shows an example of the two-screen control routine of FIG. In the case of two-screen display, image data must be compressed in the vertical direction by dividing and recording the area of the reproduction buffer memory into upper and lower parts.
The vertical compression of the image data is performed by a method of skipping every other horizontal line from the main memory 4 in the vertical direction and reading it out. At this time, in the vertical address generation permission / rejection 142 NV of the two-screen address generation unit, a value twice larger than the value of the vertical address designated from the horizontal / vertical counter 12 to the reproduction buffer memory 5 is set as the vertical address of the image data in the main memory 4. Will be applied. Whether the recording of the upper one screen has been completed can be known by detecting the falling edge of the most significant bit from the vertical address generator 142V of the two-screen address generator. Vertical address generator 1
If an overflow occurs from 42V, the microcomputer 9 applies the page address of the second image data to the address of the main memory 4 and performs the reading and recording operations on the second image data.

First, a flag indicating that recording is being performed is made in the reproduction buffer memory 5 by the multiplex screen control unit (step 900). The operation display flag is used when the microcomputer 9 checks whether or not the multi-screen control unit 10 operates. The page address of the designated image data is applied to the address bus of the main memory 4 (step 910). The horizontal / vertical counter 12 is cleared to initialize the operation of the horizontal / vertical counter 12 (step 920). The horizontal / vertical counter 12 is operated to start the reading operation from the main memory 4 and the recording operation to the reproduction buffer memory 5 (step 930). The vertical overflow signal is checked, and the process waits until the recording of the first image data is completed (step 940). If the recording operation of the first image data is completed, the page address of the second screen is applied to the address bus of the main memory 4 (step 950). The operation of the horizontal / vertical counter 12 is restarted, and the reading operation from the main memory 4 and the recording operation to the reproduction buffer memory 5 are restarted (step 960). The end signal from the horizontal / vertical counter 12 is checked to wait for the completion of the recording in the reproduction buffer memory 5 (step 970). When the recording operation is completed, the operation display flag is reset, and the two-screen display routine ends (steps 980-990).

FIGS. 10 and 11 show an example of the four-screen control routine of FIG. In the case of a four-screen display, the area of the reproduction buffer memory is divided into two parts in the vertical and horizontal directions and displayed, so that data compression in the horizontal and vertical directions must be performed. The compression of image data in the vertical direction is performed by a method of skipping every other pixel on a horizontal line on the main memory 4 and reading it out. At this time, the address values generated by the horizontal and vertical address generators of the four-screen address generator are applied as read addresses of the main memory 4. Whether the recording of the first horizontal line on the first screen is completed can be known by detecting the falling edge of the most significant bit from the horizontal address generation state 144H of the four-screen address generation unit 144. 4-screen address generator 14
4 generates a page address of the second image data to the address bus of the main memory 4 to read and execute the second image data from the first horizontal line. The recording operation will be performed. In the reading of the second image, if an overflow occurs from the horizontal address generation unit 144H of the four-screen address generation unit 144, the microcomputer 9 applies the page address of the first image to the address bus of the main memory 4 and outputs the first image. The reading and recording operations for the next horizontal line of data will be performed. This is accomplished by reading every other horizontal line from the main memory 4 in the vertical direction to compress the image data in the vertical direction. At this time, the vertical address value generated from the vertical address generator 144V of the four-screen address generator is applied as a read address of the first and second image data of the main memory 4. When the reading and recording operations for the final horizontal lines of the first and second images are completed in the same manner as described above, the microcomputer 9 applies the page address of the third image data to the address bus of the main memory 4 and The reading and recording operations for the fourth image data are performed. The completion of the recording of the first and second image data can be determined by detecting the falling edge of the most significant bit (MSB) from the vertical address generator 144V of the four-screen address generation 144. If an overflow signal is generated from the vertical address generation unit 144V of the unit 144, the microcomputer 9 applies the page address of the third image to the address bus of the main memory 4 and performs reading and recording operations on the third image.

First, a flag indicating that recording to the reproduction buffer memory is being performed is set by the multiplex screen control unit (step 1000). The operation display flag is used when the microcomputer 9 checks whether or not the multi-screen control unit 10 operates.
The page address of the first image data is applied to the address bus of the main memory 4 (step 1010). The horizontal / vertical counter 1 for initializing the operation of the horizontal / vertical counter 12
2 is reset (step 1020). The horizontal / vertical counter 12 is operated to start the reading operation from the main memory 4 and the recording operation in the buffer memory 5 for reproduction (step 1030). 4
The horizontal overflow of the screen address generator 144 is monitored, and the reading and recording of the first horizontal line of the first image data is completed (step 1040). When the recording of the first image data on the horizontal line is completed, the page address of the second screen is applied to the address bus (step 1050), and the horizontal / vertical counter 12 is operated to operate the first horizontal line of the second image data. Line reading and recording are performed (step 1060). It monitors the horizontal overflow and waits for the completion of the recording for the first horizontal line of the second image (step 1070). If the recording of the first horizontal line of the second image data is completed, it is checked whether a vertical overflow has occurred (step 1080). If the vertical overflow does not occur, the page address of the first image data is applied to the address bus of the main memory 4 (step 1090). The operation of the horizontal / vertical counter 12 is restarted (step 1100), and the process returns to step 1040 for monitoring horizontal overflow. The reading and recording operations of the first image data and the second image data up to the last horizontal line are performed by repeating the above steps (1040-1100). If a vertical overflow is detected from step 1080, the page address of the third image data is applied to the address bus (step 1110). The reading and recording processes of the third and fourth images are exactly the same as the reading and recording processes of the first and second images (1120-11).
90 stages). However, if a vertical overflow occurs after the last horizontal line recording of the fourth image in step 1170, the horizontal / vertical counter is cleared, the operation display flag is reset, and the four-screen control routine ends (1200-1).
210 stage).

FIG. 12 shows a screen state displayed on the image display unit according to the present invention.

[0025]

According to the present invention, a plurality of screens can be displayed on the screen display unit, and time can be saved in retrieving a plurality of image data recorded in the main memory of the electronic still camera.

It should also be appreciated that the invention can be used with devices that store image data on main memory, such as a color video printer, as has been made clear by the description of the invention.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a recording screen of a conventional electronic still camera.

FIG. 2 is a diagram illustrating a screen area division state of a main memory illustrated in FIG. 1;

FIG. 3 is a block diagram of a multi-screen display circuit according to the present invention.

FIG. 4 is a block diagram of a multi-screen control unit including a main memory, a buffer memory for reproduction, and a microcomputer shown in FIG. 3;

FIG. 5 is an example of a multi-screen display address generator shown in FIG. 4;

FIG. 6 is an example of a flowchart of a multiple screen control method according to the present invention.

FIG. 7 is an example of a search display routine shown in FIG. 6;

FIG. 8 is an example of a one-screen display routine shown in FIG. 7;

FIG. 9 is an example of a two-screen display routine shown in FIG. 7;

FIG. 10 is a flowchart illustrating an example of a four-screen display routine illustrated in FIG. 7;

FIG. 11 is a flowchart following FIG. 10;

FIG. 12 shows a screen state displayed on the screen display unit according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Video input part 2 A / D converter 3 Buffer memory 4 Main memory 5 Reproduction buffer memory 6 D / A converter 7 Image display part 8 Screen selection part 9 Microcomputer 10 Multiple screen control part 11 Flip-flop 12 Horizontal / vertical counter 13 Multiplexer 15 Horizontal / vertical overflow detector 14N, 141, 142, 143, 144 Screen address generator

Claims (8)

(57) [Claims] An electronic still camera which digitizes a video signal, stores it in a main memory, and displays an image by a reproducing means, for receiving an input of an image to be displayed in a search mode or an input of a search end command. A screen selection unit, a microcomputer that performs predetermined control in response to input of an instruction from the screen selection unit, and receives a read address for one screen or a plurality of image data recorded in the main memory in the search mode under the control of the microcomputer. look including a multiplex screen control unit for generating the multi-screen control unit address of the reproduction buffer memory
The horizontal / vertical counter for designation and the most significant bit of the output value of the horizontal / vertical counter are checked.
Horizontal and vertical overflow detection
And a flip-flop for temporarily stopping the horizontal and vertical counters
And multiple multiplex screen addresses for each screen state
Unit and the multi-screen address generation under the control of the microcomputer
Multiplexer that selectively outputs one of the outputs of the
Multiple screen control circuit of the electronic still camera, which comprises. 2. A read address designation for one screen or a plurality of image data recorded in the main memory is performed by applying a page address on the main memory from the microcomputer and applying a read address to the image data recorded on each page from the multiplex screen control unit. 2. The multiple screen control circuit for an electronic still camera according to claim 1, wherein a read address is specified. 3. The multi-screen address generator according to claim 1, wherein the multi-screen address generator provides a count value that is an even multiple of an input clock.
A counter, a second counter for providing a count value of an integral multiple, and the first
A first multiplier connected to the counter; a first adder for adding the output values of the first counter and the second counter; a horizontal address generator having a horizontal overflow detector; A third counter providing an even multiple count value, a fourth counter providing an integer multiple count value, a second multiplier connected to the third counter, and a third counter and a fourth counter. A second adder for adding an output value, a vertical address generator including a vertical overflow detector, and an OR gate for performing an OR operation on outputs of the horizontal overflow detector and the vertical overflow detector. 2. The multiple screen control circuit of the electronic still camera according to 1 . 4. The flip-flop receives a clock for driving a horizontal / vertical counter and a multiplexed screen address generator, and supplies a clock to the horizontal / vertical counter and a multiplexed screen address generator when a horizontal or vertical overflow is detected. 2. The multi-screen control circuit of an electronic still camera according to claim 1, wherein the control is interrupted. 5. The flip-flop according to claim 1, wherein a clock supply to a horizontal / vertical counter and a multi-screen address generator is restarted in response to a clock supply control signal from a microcomputer. Item 5. A multiple screen control circuit for an electronic still camera according to Item 4 . 6. The horizontal overflow detection section or the vertical overflow detection section outputs the last of one horizontal or vertical line of image data recorded in the main memory from the horizontal address generation section or the vertical address generation section of the multiplex screen address generation section. 4. The multiple screen control circuit for a still camera according to claim 3, wherein the circuit is configured to detect a portion. 7. The multi-screen control circuit of an electronic still camera according to claim 4, wherein said horizontal overflow detector is configured to clear a first counter and a second counter when a horizontal overflow is detected. . 8. The multi-screen control circuit of an electronic still camera according to claim 4, wherein said vertical overflow detector is configured to clear a third counter and a fourth counter when a vertical overflow is detected. .