KR920015574A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

Info

Publication number
KR920015574A
KR920015574A KR1019910001588A KR910001588A KR920015574A KR 920015574 A KR920015574 A KR 920015574A KR 1019910001588 A KR1019910001588 A KR 1019910001588A KR 910001588 A KR910001588 A KR 910001588A KR 920015574 A KR920015574 A KR 920015574A
Authority
KR
South Korea
Prior art keywords
metal
etching
entire surface
metal layer
insulating
Prior art date
Application number
KR1019910001588A
Other languages
Korean (ko)
Other versions
KR930011503B1 (en
Inventor
박종호
박창수
이상인
손정하
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910001588A priority Critical patent/KR930011503B1/en
Priority to JP3170607A priority patent/JPH04249345A/en
Publication of KR920015574A publication Critical patent/KR920015574A/en
Application granted granted Critical
Publication of KR930011503B1 publication Critical patent/KR930011503B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

반도체장치의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a도~제2i도는 본 발명에 의한 금속배선 공정순서를 나타낸 단면도.2a to 2i are sectional views showing the metal wiring process sequence according to the present invention.

Claims (7)

a. 반도체 기판상에 피복된 제1절연막에 콘택홀을 형성하는 공정; b. 상기 콘택홀 형성후, 상기 콘택홀이 완전해 매립되도록 전표면에 제1금속층을 형성하는 공정; c. 상기 제1금속층을 에치백공정으로 전면식각하여 상기 제1절연막상의 제1금속층을 완전히 제거하고, 상기 콘택홀 내에만 상기 제1절연막과 거의 동일 높이로 제1금속층을 남기는 공정; d. 상기 전면식각후, 결과물의 전표면에 제2절연막을 균일하게 피복하는 공정; e. 상기 피복공정후, 상기 제2절연막상에 포토레지스트를 덮고 금속배선용 역패턴 마스크를 적용하여 상기 포토레지스트를 패터닝하는 공정; f. 상기 포토레지스패턴을 식각마스크로 사용하여 상기 제2절연막을 식각하여 절연막패턴을 형성하고 포토레지스트래턴을 제거하는 공정; g. 상기 식각공정후, 제2절연막패턴 사이의 요홈이 완전히 매립되도록 전표면에 제2금속층을 형성하는 공정; h. 상기 제2금속층을 에치백공정으로 전면식각하여 상기 제2절연막패턴상의 제2금속층을 완전히 제거하고 상기 제2절연막패턴 사이의 요홈내에만상기 제2절연맥패턴과 거의 동일한 높이로 제2금속층을 남기는 공정; 및 i. 상기 전면식각후, 결과물의 전표면에 제3절연막을 그 표면이 대체적으로 평탄하게 피복하는 공정을 구비하는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.a. Forming a contact hole in the first insulating film coated on the semiconductor substrate; b. Forming a first metal layer on the entire surface of the contact hole so that the contact hole is completely filled after the contact hole is formed; c. Etching the entire first metal layer by an etch back process to completely remove the first metal layer on the first insulating layer, and leaving the first metal layer at substantially the same height as the first insulating layer only in the contact hole; d. After the entire surface etching, uniformly coating the second insulating film on the entire surface of the resultant product; e. After the coating step, covering the photoresist on the second insulating film and patterning the photoresist by applying an inverse pattern mask for metal wiring; f. Etching the second insulating layer by using the photoresist pattern as an etching mask to form an insulating layer pattern and to remove photoresist lattice; g. After the etching process, forming a second metal layer on the entire surface such that the grooves between the second insulating film patterns are completely filled; h. Etching the entire surface of the second metal layer by an etch back process to completely remove the second metal layer on the second insulating layer pattern, and to leave the second metal layer at substantially the same height as the second insulating vein pattern only in the grooves between the second insulating layer patterns. fair; And i. And after the entire surface etching, covering the entire surface of the resultant surface with a third insulating film substantially flat. 제1항에 있어서, 상기 제1 및 제2금속층을 피복하는 공정은 스퍼터링 또는 CVD 방법중 어느 하나인 것을 특징으로 하는반도체 장치의 금속배선 형성방법.The method of claim 1, wherein the coating of the first and second metal layers is any one of sputtering and CVD methods. 제1항에 있어서, 상기 제1 및 제2금속층은 알루미늄에 Si, Cu, Ti, Pd, Hf 또는 B가 소량첨가된 알루미늄 합금인것을 특징으로 하는 반도체장치의 금속 배선 형성방법.2. The method of claim 1, wherein the first and second metal layers are aluminum alloys in which a small amount of Si, Cu, Ti, Pd, Hf, or B is added to aluminum. 제1항에 있어서, 상기 제1 및 제2금속층은 고융점금속 또는 고융점 금속실리사이드로 된 장벽층과 알루미늄합금의 적층막으로 된 것을 특징으로 하는 반조체 장치의 금속배선 형성방법.The method of claim 1, wherein the first and second metal layers are formed of a barrier film made of a high melting point metal or a high melting point metal silicide and a laminated film of an aluminum alloy. 제4항에 있어서, 상기 고융점금속 또는 고융점금속 실리사이드는 Ti/TiN, MoSix, TiW, TiSix, 또는 W등인 것을 특징으로하는 반도체 장치의 금속배선 형성방법.The method of claim 4, wherein the high melting point metal or the high melting point metal silicide is Ti / TiN, MoSix, TiW, TiSix, W, or the like. 제1항에 있어서, 상기 제2 및 제3절연막은 SixNy, SixOyNz, USG.PSG 또는 BPSG로 된 것을 특징으로 하는 반도체 장치의금속배선 형성방법.The method of claim 1, wherein the second and third insulating films are made of SixNy, SixOyNz, USG.PSG, or BPSG. 제1항에 있어서, 상기 제1금속층은 텅스텐 또는 텅스텐 실리사이드인 것을 특징으로 하는 반도체 장치의 금속배선 형성방법.The method of claim 1, wherein the first metal layer is tungsten or tungsten silicide. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001588A 1991-01-30 1991-01-30 Metal wire forming method of semiconductor KR930011503B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910001588A KR930011503B1 (en) 1991-01-30 1991-01-30 Metal wire forming method of semiconductor
JP3170607A JPH04249345A (en) 1991-01-30 1991-06-14 Method of forming metallic wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001588A KR930011503B1 (en) 1991-01-30 1991-01-30 Metal wire forming method of semiconductor

Publications (2)

Publication Number Publication Date
KR920015574A true KR920015574A (en) 1992-08-27
KR930011503B1 KR930011503B1 (en) 1993-12-08

Family

ID=19310500

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910001588A KR930011503B1 (en) 1991-01-30 1991-01-30 Metal wire forming method of semiconductor

Country Status (2)

Country Link
JP (1) JPH04249345A (en)
KR (1) KR930011503B1 (en)

Also Published As

Publication number Publication date
JPH04249345A (en) 1992-09-04
KR930011503B1 (en) 1993-12-08

Similar Documents

Publication Publication Date Title
KR950025957A (en) Semiconductor device having wiring of laminated structure and manufacturing method
KR960039281A (en) Wiring Structure of Semiconductor Device and Manufacturing Method Thereof
KR940010277A (en) Semiconductor device of multi-layered wiring structure and manufacturing method thereof
KR940020531A (en) Manufacturing method of metal plug in contact hole
KR920015574A (en) Metal wiring formation method of semiconductor device
KR920015491A (en) Metal wiring formation method of semiconductor device
KR970018413A (en) Method for forming multilayer wiring of semiconductor device
KR970008491A (en) Method for forming multilayer wiring of semiconductor device
KR920010864A (en) How to Form Flattened Metal Wiring
KR950009965A (en) Method of forming interlayer insulating film of semiconductor device
KR960035969A (en) Method for forming metal wiring
KR950021425A (en) How to Form Multilayer Metal Wiring
KR930011196A (en) Method for forming multilayer wiring of semiconductor device
KR970030658A (en) Wiring Formation Method of Semiconductor Device
KR970052945A (en) Metal wiring formation method of semiconductor device
JPS636847A (en) Manufacture of semiconductor device
JPH08274098A (en) Semiconductor device and its manufacture
KR930001390A (en) Metal wiring film formation method
KR940016669A (en) Method of forming multi-layer metal wiring of semiconductor device
KR970052334A (en) Metal wiring formation method of semiconductor device
KR960002681A (en) How to Form Multilayer Metal Wiring
KR960026628A (en) Metal wiring formation method
KR960043119A (en) Via hole formation method of semiconductor device
KR960026233A (en) Metal wiring method of semiconductor device
KR970052331A (en) Metal wiring formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20071203

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee