KR920014297A - Signal terminal group bus triple signal monitoring circuit of electronic exchange - Google Patents

Signal terminal group bus triple signal monitoring circuit of electronic exchange Download PDF

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Publication number
KR920014297A
KR920014297A KR1019900022826A KR900022826A KR920014297A KR 920014297 A KR920014297 A KR 920014297A KR 1019900022826 A KR1019900022826 A KR 1019900022826A KR 900022826 A KR900022826 A KR 900022826A KR 920014297 A KR920014297 A KR 920014297A
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KR
South Korea
Prior art keywords
signal
bus
triple
terminal group
signal terminal
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KR1019900022826A
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Korean (ko)
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KR930006862B1 (en
Inventor
김도영
이형호
박원기
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019900022826A priority Critical patent/KR930006862B1/en
Publication of KR920014297A publication Critical patent/KR920014297A/en
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Publication of KR930006862B1 publication Critical patent/KR930006862B1/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

내용 없음No content

Description

전자교환기의 신호단말 그룹 버스 삼중화 신호 감시회로Signal terminal group bus triple signal monitoring circuit of electronic exchange

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 공통선 신호장치내의 신호 단말 그룹구성도, 제2도는 본 발명이 적용되는 신호단말그룹 유지보수 회로의 프로세서부 구성도, 제3도는 본 발명이 적용되는 신호단말 그룹 유지보수 회로의 로직부 구성도, 제4도는 본 발명을 나타내는 구성도.1 is a block diagram of a signal terminal group in a common line signal apparatus to which the present invention is applied, FIG. 2 is a block diagram of a processor unit of a signal terminal group maintenance circuit to which the present invention is applied, and FIG. 3 is a signal terminal group to which the present invention is applied. Fig. 4 is a block diagram showing the logic portion of the maintenance circuit.

Claims (3)

전자교환기의 신호단말 그룹버스 삼중화 신호 감시회로에 있어서, 신호단말 그룹버스신호를 각각 삼중화하여 송수신하여 동기신호(SYNC)와 망출력 클럭(NCLKOUT: Network Clock OUT) 및 상위블럭에서 수신되는 데이터(RXD)를 수신하여 삼중화 버스 인터페이스 수단(40), 상기 삼중화 버스 인터페이스 수단(40)에 연결되어 있으며 망출력 클럭(NCLKOUT)을 수신하며 전송데이터(TXD)와 데이터 송신버스 점유신호와 동기신호및 데이터 송수신 클럭(NCLK)을 송신하는 삼중화 버스 변환수단(41), 상기 삼중화 버스 인터페이스 수단(40)에 연결되어 데이터 송수신 클럭1(NCLK1)을 수신하며 인터럽트가 발생되도록 하는 신호(LFLT)와 장애 발생정보를 출력하는 삼중화 버스장애 검출수단(42), 상기 삼중화 버스 장애 검출수단(42)에 연결되며 래치회로로 구성되어 인터럽트 발생신호(LEFT)가 입력되면 인터럽트 장애신호(INTLINFLT: Interrupt Line Fault)를 발생시키는 삼중화버스 인터럽트 발생수단(43), 상기 삼중화 버스 장애 검출수단(42)에 연결되며 래치회로로 구성되어 장애 발생정보를 수신한 후 발생부위 정보를 선로장애리드(LINFLTRD: Line Fault Read)신호로 검출하여 내부 데이티버스(IDB0-IDB7)을 통해 출력하는 삼중화버스 장애상태 읽음수단(44)로 구성됨을 특징으로 하는 전자교환기의 신호단말 그룹 삼중화 신호 감시회로.In the signal terminal group bus triplex signal monitoring circuit of an electronic switching system, data received from a synchronization signal (SYNC), a network output clock (NCLKOUT) and an upper block by triplexing and transmitting the signal terminal group bus signals respectively. (RXD) receives and is connected to the triplex bus interface means 40, the triplex bus interface means 40, receives the network output clock (NCLKOUT), the transmission data TXD and the data transmission bus occupied signal And sync signal And a signal LFLT connected to the triple bus conversion means 41 for transmitting the data transmission / reception clock NCLK and the triple bus interface means 40 to receive the data transmission / reception clock 1 NCLK1 and generating an interrupt. Is connected to the triple bus failure detecting means 42 and outputs the fault occurrence information, and is configured as a latch circuit, and the interrupt generation signal LEFT is inputted, the interrupt fault signal INTLINFLT: It is connected to the triple bus interrupt generating means 43 and the triple bus fault detecting means 42 for generating an Interrupt Line Fault. LINFLTRD: Signal terminal of an electronic exchange comprising a triple bus fault status reading means (44) which is detected as a line fault read (LINFLTRD) signal and outputted through an internal data bus (IDB0-IDB7). Triple screen signal monitoring circuit. 제1항에 있어서, 상기 삼중화 버스 변환수단(41)은 신호단말 그룹버스와 동일한 신호를 입력으로 하여 신호단말 유지보수장치 로직부의 각 블럭에 동일위상의 단일신호를 공급하도록 PAL(Programmable Array Logic)로 구성됨을 특징으로 하는 전자교환기의 신호단말 그룹 버스 삼중화 신호 감시회로.The PAL (Programmable Array Logic) according to claim 1, wherein the triple bus conversion means (41) inputs the same signal as the signal terminal group bus and supplies a single signal of the same phase to each block of the logic terminal of the signal terminal maintenance apparatus. The signal terminal group bus triplet signal monitoring circuit of an electronic exchange, comprising: a). 제1항에 있어서, 상기 삼중화 버스 장애 검출수단(42)은 신호단말 그룹버스와 동일한 신호를 입력으로 하여 삼중화된 각 신호의 장애발생 여부 및 장애 발생부위를 출력할 수 있도록 PAL로 구성됨을 특징으로 하는 신호단말 그룹 버스 삼중화 신호 감시회로.The method of claim 1, wherein the triple bus failure detecting means (42) is configured as a PAL so as to output a failure state and a failure occurrence area of each triplet signal by inputting the same signal as the signal terminal group bus. Signal terminal group bus triplexed signal monitoring circuit. ※ 참고사항 : 최초출원내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900022826A 1990-12-31 1990-12-31 Triple modular redundency method KR930006862B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022826A KR930006862B1 (en) 1990-12-31 1990-12-31 Triple modular redundency method

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Application Number Priority Date Filing Date Title
KR1019900022826A KR930006862B1 (en) 1990-12-31 1990-12-31 Triple modular redundency method

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KR920014297A true KR920014297A (en) 1992-07-30
KR930006862B1 KR930006862B1 (en) 1993-07-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293364B1 (en) * 1997-12-27 2001-07-12 박종섭 Communication method between main processor and sub processors using common bus in mobile switching center

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293364B1 (en) * 1997-12-27 2001-07-12 박종섭 Communication method between main processor and sub processors using common bus in mobile switching center

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Publication number Publication date
KR930006862B1 (en) 1993-07-24

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