KR920013915A - Stable Power-On Reset Circuit - Google Patents

Stable Power-On Reset Circuit Download PDF

Info

Publication number
KR920013915A
KR920013915A KR1019900022444A KR900022444A KR920013915A KR 920013915 A KR920013915 A KR 920013915A KR 1019900022444 A KR1019900022444 A KR 1019900022444A KR 900022444 A KR900022444 A KR 900022444A KR 920013915 A KR920013915 A KR 920013915A
Authority
KR
South Korea
Prior art keywords
output
reset
signal
power
waveform shaping
Prior art date
Application number
KR1019900022444A
Other languages
Korean (ko)
Other versions
KR940000224B1 (en
Inventor
박종훈
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900022444A priority Critical patent/KR940000224B1/en
Publication of KR920013915A publication Critical patent/KR920013915A/en
Application granted granted Critical
Publication of KR940000224B1 publication Critical patent/KR940000224B1/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Landscapes

  • Electronic Switches (AREA)

Abstract

내용 없음No content

Description

안정된 파워 온 리세트 회로Stable Power-On Reset Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 안정된 파워 온 리세트 회로도, 제4도(가) 내지 (아)는 제3도에 따른 각부 동작 타이밍.3 is a stable power-on reset circuit diagram according to the present invention, and FIGS.

Claims (1)

외부 R ●C 시정수를 통해 파워(VDD)은 신호를 입력받아 파형정형화부를(11)를 통해 구형파 신호로 리세트 신호출력을 하는 파워 온 리세트 회로에 있어서, 상기 파형정형화부(11)의 출력을 인버터(I11)를 통해 인가받아 리세트 신호가 소정시간 지연되는 글리치 출력을 발생하는 글리치 발생부(14)와, 상기 인버터(I11)의 출력 및 최종 리세트 출력(Vout)을 인가받아 소정주기의 펄서를 발생하는 발진부(13)와, 상기 글리치 발생부(14)의 제어에 따라 동작하여 상기 발진부(13)의 발진출력을 1주기 지연시켜 출력하는 분주회로(15)의 출력을 클럭신호로 인가받고 상기 파형정형화부(11)의 출력을 클리어신호(CD1)로 인가받아 비반전 출력(Q1)을 최종파워 온 리세트 신호로 출력(Vout)하는 출력 플립플롭(13)으로 구성하여 된 것을 특징으로 하는 안정된 파워 온 리세트 회로.Through the external R ● number C constant power (V DD) is in receiving a signal in a power-on reset circuit to the reset signal output by the square wave signal through the waveform shaping section 11, the waveform shaping section 11 and receive the output is applied through an inverter (I 11), the reset signal glitches unit 14 for generating a glitch output that is delayed a predetermined time, the output and end the reset output (Vout) of said inverter (I 11) The output of the frequency divider circuit 15 which is applied under the control of the oscillator 13 and the glitch generator 14 to generate a pulse of a predetermined period by delaying the oscillation output of the oscillator 13 by one cycle. Is applied as a clock signal and the output of the waveform shaping unit 11 is applied as a clear signal CD 1 to output the non-inverted output Q 1 as a final power-on reset signal (Vout). Stable power-on reset, characterized in that consisting of Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022444A 1990-12-29 1990-12-29 Power-on reset circuit for stable KR940000224B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022444A KR940000224B1 (en) 1990-12-29 1990-12-29 Power-on reset circuit for stable

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022444A KR940000224B1 (en) 1990-12-29 1990-12-29 Power-on reset circuit for stable

Publications (2)

Publication Number Publication Date
KR920013915A true KR920013915A (en) 1992-07-30
KR940000224B1 KR940000224B1 (en) 1994-01-12

Family

ID=19308947

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022444A KR940000224B1 (en) 1990-12-29 1990-12-29 Power-on reset circuit for stable

Country Status (1)

Country Link
KR (1) KR940000224B1 (en)

Also Published As

Publication number Publication date
KR940000224B1 (en) 1994-01-12

Similar Documents

Publication Publication Date Title
KR930003551A (en) Instant test mode designation circuit
JPS55150148A (en) Cue signal generating circuit
KR910008964A (en) Frequency division circuits where the division ratio can be changed
KR910005566A (en) Programmable Square Wave Generator
KR920013915A (en) Stable Power-On Reset Circuit
KR900019368A (en) Circuit device for supplying periodic parabolic signals
KR960008476A (en) Microcomputer reset device
KR910013764A (en) Polarotar Pulse Generator Circuit of Satellite Broadcasting Receiver
KR900002245A (en) 4-head switching pulse generator
JPS55150028A (en) Clock circuit for digital operation processor
KR940025166A (en) One Pulse Generator
KR940012090A (en) Clock divider
KR900702709A (en) Voice signal demodulation circuit
KR920015709A (en) Overlap prevention clock pulse generator
JPS6447121A (en) Pulse width modulation signal generating circuit
KR970072668A (en) Pulse generator
KR970059926A (en) Glitch signal output prevention circuit of MC output
KR970013690A (en) Glitch-independent control signal generator
KR910015112A (en) Oscillator (VCO)
KR950028317A (en) Programmable Frequency Divider Using Memory Devices
KR890006056A (en) Sawtooth Wave Generator for Vertical Deflection
KR930011432A (en) Sub-step control signal generation circuit using step pulse interval
KR950016272A (en) Clock synchronization circuit
KR910005127A (en) 'DB6' data pattern generator
KR920017354A (en) Pulse generator with edge detection

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021223

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee