KR920013157A - Transmission and reception data matching device - Google Patents

Transmission and reception data matching device Download PDF

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Publication number
KR920013157A
KR920013157A KR1019900020520A KR900020520A KR920013157A KR 920013157 A KR920013157 A KR 920013157A KR 1019900020520 A KR1019900020520 A KR 1019900020520A KR 900020520 A KR900020520 A KR 900020520A KR 920013157 A KR920013157 A KR 920013157A
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KR
South Korea
Prior art keywords
transmission
channel
matching device
reception
data matching
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KR1019900020520A
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Korean (ko)
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KR960001246B1 (en
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윤성표
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정용문
삼성전자 주식회사
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Priority to KR1019900020520A priority Critical patent/KR960001246B1/en
Publication of KR920013157A publication Critical patent/KR920013157A/en
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Publication of KR960001246B1 publication Critical patent/KR960001246B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

내용 없음No content

Description

송수신 데이타 정합장치Transmission and reception data matching device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 송수신 데이타 정합장치의 구성도, 제2도는 제1도에 따른 송수신 데이타 정합장치의 일 실시예시도, 제3도는 제2도에 따른 송수신 데이타 정합장치의 동작파형도.1 is a block diagram of a transmission and reception data matching device according to an embodiment of the present invention, FIG. 2 is an embodiment of the transmission and reception data matching device according to FIG. 1, and FIG.

Claims (6)

상위비트는 채널값을 계수하고 하위비트는 채널당 데이타수를 계수하는 계수부(10)와, 슬레이브 자신의 채널값과 송수신 채널값을 비교하는 비교부(20)와, 각 슬레이브의 채널값을 지정하는 채널지정부(30)와, 상기 비교부(20)의 출력신호로 부터 데이타 스트림의 입출력 신호를 제어하는 스위칭부(40)와, 주클럭을 분주하는 분주부(50)와, 데이타 스트림을 특성별로 분류하는 디멀티플렉서부(60)와, 각 채널의 데이타 스트림을 멀티 플렉싱하는 멀티플렉서부(70)를 포함함을 특징으로 하는 송수신 데이타 정합장치.The upper bit designates the channel value and the lower bit designates the counting unit 10 for counting the number of data per channel, the comparator 20 for comparing the slave's own channel value with the transmission / reception channel value, and the channel value of each slave. The channel designator 30 to control the input / output signal of the data stream from the output signal of the comparator 20, the divider 50 to divide the main clock, and the data stream. And a multiplexer (70) for multiplexing the data streams of each channel. 제1항에 있어서, 계수부(10)는 2진 계수기를 사용하여 상위비트를 채널값으로 하고 하위비트를 채널별 송수신비트의 수로 계수하는 것을 특징으로 하는 송수신 데이타 정합장치.2. The transmission and reception data matching device according to claim 1, wherein the counting unit (10) counts the upper bits as channel values and the lower bits as the number of transmission / reception bits for each channel using a binary counter. 제1항에 있어서, 계수부(10)는 입출력 전송속도의 2배인 주클럭(MLCK)을 입력신호로 사용하는 것을 특징으로 하는 송수신 데이타 정합장치.The transmission / reception data matching device according to claim 1, wherein the counter (10) uses a main clock (MLCK), which is twice the input / output transmission speed, as an input signal. 제1항에 있어서, 계수부(10)는 마스터로 부터의 프레임 동기신호(FS)를 이용하여 리세트되는 것을 특징으로 하는 송수신 데이타 정합장치.The transmission / reception data matching device according to claim 1, wherein the counting unit (10) is reset using a frame synchronization signal (FS) from the master. 제1항에 있어서, 채널지정부(30)는 스위치 대신 래치로 구현하여 각 슬레이브의 제어단에서 채널값을 가변할수 있도록 하는 것을 특징으로 하는 송수신 데이타 정합장치.The transmission and reception data matching device of claim 1, wherein the channel designation unit (30) implements a latch instead of a switch so as to change a channel value at a control terminal of each slave. 제1항에 있어서, 디멀티플렉서부(60)는 주클럭(MCLK)를 받아 수신데이타 스트림의 해당 블럭에만 입력되도록 하는 것을 특징으로 하는 송수신 데이타 정합장치.The apparatus of claim 1, wherein the demultiplexer unit (60) receives a main clock (MCLK) and inputs only the corresponding block of the received data stream. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900020520A 1990-12-13 1990-12-13 An apparatus for data matching in data transmission interface KR960001246B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900020520A KR960001246B1 (en) 1990-12-13 1990-12-13 An apparatus for data matching in data transmission interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020520A KR960001246B1 (en) 1990-12-13 1990-12-13 An apparatus for data matching in data transmission interface

Publications (2)

Publication Number Publication Date
KR920013157A true KR920013157A (en) 1992-07-28
KR960001246B1 KR960001246B1 (en) 1996-01-24

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Application Number Title Priority Date Filing Date
KR1019900020520A KR960001246B1 (en) 1990-12-13 1990-12-13 An apparatus for data matching in data transmission interface

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KR960001246B1 (en) 1996-01-24

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