KR920011063A - Noise Signal Reduction Circuit of Semiconductor Device - Google Patents

Noise Signal Reduction Circuit of Semiconductor Device Download PDF

Info

Publication number
KR920011063A
KR920011063A KR1019900018787A KR900018787A KR920011063A KR 920011063 A KR920011063 A KR 920011063A KR 1019900018787 A KR1019900018787 A KR 1019900018787A KR 900018787 A KR900018787 A KR 900018787A KR 920011063 A KR920011063 A KR 920011063A
Authority
KR
South Korea
Prior art keywords
node
noise signal
input buffer
transistor
gate
Prior art date
Application number
KR1019900018787A
Other languages
Korean (ko)
Other versions
KR930008649B1 (en
Inventor
서영호
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900018787A priority Critical patent/KR930008649B1/en
Publication of KR920011063A publication Critical patent/KR920011063A/en
Application granted granted Critical
Publication of KR930008649B1 publication Critical patent/KR930008649B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음No content

Description

반도체 장치의 잡음신호 제거회로Noise Signal Reduction Circuit of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 본 발명에 따른 잡음신호 제거회로를 가진 회로도, 제7도는 잡음이 발생하였을 경우의 제6도에 따른 파형도, 제8도는 정상 동작할 경우의 제6도에 따른 파형도.6 is a circuit diagram having a noise signal removing circuit according to the present invention, FIG. 7 is a waveform diagram according to FIG. 6 when noise is generated, and FIG. 8 is a waveform diagram according to FIG.

Claims (9)

입력버퍼(20)와 펄스발생기회로(40)를 구비하는 반도체 장치의 잡음신호 제거회로에 있어서, 상기 입력버퍼(20)의 출력노드(30)와 제1노드(69)사이에 접속된 하나이상의 전압강하수단(61)과, 상기 제1노드(69)와 상기 펄스발생기회로(40)의 입력측 사이에 접속된 제1반전수단(6)으로 구성됨을 특징으로 하는 잡음신호 제거회로.In the noise signal cancellation circuit of a semiconductor device having an input buffer 20 and a pulse generator circuit 40, one connected between the output node 30 and the first node 69 of the input buffer 20. And a first inverting means (6) connected between the voltage drop means (61) and the input side of the first node (69) and the pulse generator circuit (40). 제1항에 있어서, 상기 전압강하수단(61)이 다이오드 접속된 앤모오스 트랜지스터임을 특징으로 하는 잡음신호 제거회로.2. The noise signal removal circuit according to claim 1, wherein said voltage drop means (61) is a diode-connected NMOS transistor. 제1항에 있어서, 상기 제1반전수단(6)이 직렬접속된 피모오스 트랜지스터(62)와 엔모오스 트랜지스터(63)로 구성됨을 특징으로 하는 잡음신호 제거회로.The noise signal removal circuit according to claim 1, wherein said first inverting means (6) comprises a PMOS transistor (62) and an enMOS transistor (63) connected in series. 제2항 또는 제3항에 있어서, 상기 저압 강하수단(61)에 의해 제1노드(69)의 전압이 잡음발생시는 상기 제1반전수단(64)의 로딕 드레쉬홀드 전압값보다 더 작은 값을 가지고, 정상동작시는 상기 제1반전수단(64)의 로직 드레쉬홀드 전압값보다 더 큰 값을 가짐을 특징으로 하는 잡음신호 제거회로.4. A value according to claim 2 or 3, wherein the voltage of the first node 69 is less than the rodic threshold voltage value of the first inverting means 64 when the low voltage drop means 61 causes noise. And a value greater than the logic threshold voltage value of the first inverting means (64) during normal operation. 제1항에 있어서, 상기 입력버퍼(20)의 출력노드(30)에 접속된 제2반전수단(65)과, 상기 제2반전수단(64)의 출력측에 게이트가 접속되고 상기 제1노드(69)와 접지사이에 채널이 접속된 플다운 수단(66)을 더 구비함을 특징으로 하는 잡음신호 제거회로.According to claim 1, wherein the second inverting means 65 connected to the output node 30 of the input buffer 20, the gate is connected to the output side of the second inverting means 64 and the first node ( 69. A noise signal cancellation circuit further comprising a pull down means (66) connected between a channel (69) and ground. 제5항에 있어서, 상기 플다운수단(66)이 엔모오스 트랜지스터임을 특징으로 하는 잡음신호 제거회로.6. The noise signal removal circuit according to claim 5, wherein said down means (66) is an enMOS transistor. 제1항에 있어서, 상기 입력버퍼(20)의 출력노드(30)에 게이트가 접속되고 전원전압단과 상기 제1반전수단(64)사이에 채널이 접속된 피모오스 트랜지스터(67)와, 상기 피모오스 트랜지스터(67)의 게이트에 게이트가 접속되고 상기 제1반전수단(64)과 접지사이에 채널이 접속된 엔모오스 트랜지스터(68)를 더 구비함을 특징으로 하는 잡음신호 제거회로.The PMOS transistor 67 of claim 1, wherein a gate is connected to the output node 30 of the input buffer 20, and a channel is connected between a power supply voltage terminal and the first inverting means 64. And an NMOS transistor (68) having a gate connected to a gate of an os transistor (67) and a channel connected between the first inverting means (64) and ground. 입력버퍼(20)와 펄스발생기회로(40)를 구비하는 반도체장치의 잡음신호 제거회로에 있어서, 상기 입력버퍼(20)의 출력노드(30)와 제1노드(69)사이에 다이오드 접속된 제1엔모오스 트랜지스터(61)와, 상기 제1노드(69)에 게이트가 접속되고 서로 직렬연결된 제1피모오스 트랜지스터(62) 및 제2엔모오스 트랜지스터(63)와, 상기 제1노드(69)와 접지사이에 채널이 접속된 제3엔모오스 트랜지스터(66)와, 상기 입력버퍼(20)의 출력노드(30)와 제3엔모오스 트랜지스터(66)의 게이트 사이에 접속된 인버터(65)와, 전원전압단과 상기 제1피모오스 트랜지스터(62)의 소오스 사이에 채널이 접속되고, 상기 입력버퍼(20)의 출력노드(30)에 게이트가 접속된 제2피모오스 트랜지스터(67)와, 상기 제2엔모오스 트랜지스터(63)의 소오스가 접지사이에 채널이 접속되고 상기 입력버퍼(20)의 출력노드(30)에 게이트가 접속된 제4엔모오스 트랜지스터(68)로 구성함을 특징으로 하는 잡음신호 제거회로.In the noise signal cancellation circuit of a semiconductor device having an input buffer 20 and a pulse generator circuit 40, a diode is connected between the output node 30 and the first node 69 of the input buffer 20. A first PMOS transistor 62 and a second NMOS transistor 63 and a gate connected to the first NMOS transistor 61, the first node 69, and connected in series with each other, and the first node 69. ) And an inverter 65 connected between a third NMOS transistor 66 having a channel connected between the ground and the ground, and an output node 30 of the input buffer 20 and a gate of the third NMOS transistor 66. A second PMOS transistor 67 having a channel connected between the power supply voltage terminal and the source of the first PMOS transistor 62, and having a gate connected to the output node 30 of the input buffer 20, A channel of the source of the second NMOS transistor 63 is connected between ground and the output of the input buffer 20 is connected. Node 30 is connected to the gate of the noise signal removal, characterized in that the 4 en composed Mohs transistor 68 circuit. 제8항에 있어서, 상기 제1피모오스 트랜지스터(62)의 드레인과 상기 제2엔모오스 트랜지스터(63)의 소오스와 접속노드(70)와 상기 펄스발생기회로(40)의 입력측사이에 인버터를 더 구비할 수 있음을 특징으로 하는 잡음신호 제거회로.The inverter of claim 8, wherein an inverter is connected between the drain of the first PMOS transistor 62, the source of the second NMOS transistor 63, the connection node 70, and an input side of the pulse generator circuit 40. Noise signal cancellation circuit, characterized in that it can be further provided. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900018787A 1990-11-20 1990-11-20 Noise rejected circuit of semiconductor KR930008649B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900018787A KR930008649B1 (en) 1990-11-20 1990-11-20 Noise rejected circuit of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900018787A KR930008649B1 (en) 1990-11-20 1990-11-20 Noise rejected circuit of semiconductor

Publications (2)

Publication Number Publication Date
KR920011063A true KR920011063A (en) 1992-06-27
KR930008649B1 KR930008649B1 (en) 1993-09-11

Family

ID=19306243

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018787A KR930008649B1 (en) 1990-11-20 1990-11-20 Noise rejected circuit of semiconductor

Country Status (1)

Country Link
KR (1) KR930008649B1 (en)

Also Published As

Publication number Publication date
KR930008649B1 (en) 1993-09-11

Similar Documents

Publication Publication Date Title
KR950030487A (en) CMOS Data Output Buffer Prevents Latch-Up
KR930003556A (en) Progressive Turn-On CMOS Driver
KR900013380A (en) Voltage control circuit
KR840008097A (en) Substrate Bias Voltage Control Circuit and Method
KR900001042A (en) Semiconductor integrated circuit with CMOS inverter
KR960012471A (en) System and method with CMOS inverter circuit to reduce power consumption
KR940017201A (en) Data output buffer
KR940017190A (en) Input buffer
KR970013732A (en) Data output buffer using multi power
KR900011152A (en) Voltage drop detection and reset circuit reset circuit
KR920011063A (en) Noise Signal Reduction Circuit of Semiconductor Device
KR920003704A (en) Floating circuit driving circuit responsive to digital signal
KR950015749A (en) Power Delay Circuit of Semiconductor Memory Device
KR930014578A (en) Noise Buffer Circuit of Output Buffer
JP3055165B2 (en) Output buffer circuit
KR940020422A (en) Output buffer circuit of semiconductor memory device
KR930005370A (en) Input circuit
KR970031298A (en) Delay circuit
KR970055507A (en) Improved Output Buffer for Integrated Circuits
KR930014570A (en) Output buffer circuit
KR950022111A (en) High Speed Chip Select Buffer
KR940010511A (en) Output port circuit of semiconductor device
KR900002538A (en) Noise reduction circuit
KR970019068A (en) Low noise output buffer circuit
KR900001129A (en) High voltage switching circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010807

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee