KR920009374B1 - Method of fabricating a semiconductor device having multi-gate type transistors - Google Patents

Abstract

In manufacturing multi-gate mask ROM (MUGROM) with multi-gate type MOS TR structure, the first and second electrode layers (13,15) which are arrayed on a channel region (20) between drain and source regions (1) and (2) of a substrate (10), the method comprises ion-implanting impurities into the channel (20) to form several gate electrode layers (13) on the channel at constant intervals, forming several gate electrode layers (15) between the layers (13) on the channel such that the edges of the layers (15) cover over the edges of the layers (13) and selectively ion-implanting impurities into the enhancement channel region, thereby being self-aligned by the neighboring gate electrode layer.

Description

Self-Aligned Ion Implantation Method of Semiconductor Device with Multi-gate MOS Transistor Structure

1 is a plan view showing a cell array structure of a MUGROM.

2 is a transistor equivalent circuit diagram of a cell array of MUGROM shown in FIG.

3 is a cross-sectional view taken along the line A-A of FIG. 1 for showing the cell array structure of the MUGROM.

4 is a process flow chart showing a cell ion implantation process of a conventional MUGROM.

Figure 5 is a process flow diagram of an embodiment showing a cell ion implantation process of MUGROM according to the present invention.

6 is a process flowchart of another embodiment showing a cell ion implantation process of a MUGROM according to the present invention.

* Explanation of symbols for the main parts of the drawings

1: drain region 2: source region

3: Metal contact hole B1, B2: Bit line

W1 ~ WM: Word line (gate electrode layer) C1 ~ C3: Cell ion implantation area

M1, M3, M6: Channel Depletion MOS: Transistor

M2, M4, M5: Channel Increasing MOS Transistor

CS: common source line 10: substrate

11: first cell ion implantation mask 12: first gate oxide film

13: first gate electrode layer 14: second cell ion implantation mask

15: second gate oxide layer 16: second gate electrode layer

17: first intermediate insulating film 18: second intermediate insulating film

19: cell ion implantation mask 20: depletion channel region

21: increased channel area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a novel self-aligned ion implantation method for solving a misalignment problem in a manufacturing process of a multi-gate mask ROM (MUGROM).

Recently, as the development of semiconductor manufacturing technology and the application field of memory devices have been expanded, the development of large-capacity memory devices has been advanced. In particular, the capacity of a mask ROM, which has a simple circuit configuration and a memory cell structure that does not require a special manufacturing process, is rapidly progressing.

Mask ROM is proposed and put into practice in various ways, such as a contact mask method, a diffusion layer mask method, a NAND type ion implantation method, and a multi-gate method, according to a memory cell structure for improving the degree of integration.

Multi-gate ROM (hereinafter referred to as MUGROM) consists of a multi-gate MOS transistor similar to the structure of a charge coupled device (CCD), which constitutes a memory cell array (4 megabit full wafer). ROM IEEE 1980 International Solid State Conference, pp 150-151).

FIG. 1 is a front view showing the structure of the cell array of MUGROM, and FIG. 2 is a transistor equivalent circuit diagram of the cell array of MUGROM of FIG. A plurality of gate electrodes formed by a double polysilicon gate process are applied on the channel region between the drain region 1 and the source region 2 in the cell array of the MUGROM. A bit line B is connected to the drain region 1 through a metal contact hole 3, and the source region 2 is provided as a common source line CS. The gate electrodes are provided to the word line (W). 3 is a cross-sectional view taken along the line A-A of FIG. The hatched portion C in FIG. 1 is a portion in which an impurity opposite to the substrate, for example, an N-type impurity is implanted into the channel region under the gate electrode. Therefore, the ion-implanted portion is a channel depletion type transistor (M1, M3, M6 in FIG. 2), and the portion not in the channel is an enhancement type transistor (M2, M4, M5 in FIG. 2). Is maintained.

The channel depletion transistor and the channel increasing transistor correspond to information '1' and '0' respectively by the difference of the threshold hold voltage. Looking at the manufacturing process of such MUGROM with reference to Figure 4 as follows.

In FIG. 4A, a first cell ion is formed on a P-type (100) -oriented silicon substrate (10) in which a field oxide layer is grown to define an active region, and a P-type impurity is injected into the active region for controlling a threshold voltage. A process of injecting an N-type impurity such as arsenic (As) into the predetermined first channel region 20a by acting on the injection mask 11 is shown.

In FIG. 4B, after the first cell ion implantation process is finished, the first gate oxide layer 12 is grown, the first polysilicon layer is deposited, and the first gate mask is applied to the first gate electrode layer 13 through an etching process. ) Is formed, and then a second cell ion implantation mask 14 is applied to ion implant the N-type impurities into the predetermined second channel region 20b.

In FIG. 4C, after the second cell ion implantation process is finished, the photoresist, which is the second cell ion implantation mask 14, is removed, the second gate oxide film 15 is grown thereon, and the second polycrystalline silicon layer is deposited. A process of forming the second gate electrode layer 16 through an etching process by applying a two-gate mask is shown.

In FIG. 4D, the first and second intermediate insulating layers 17 and 18 are sequentially covered on the second gate electrode layer 16 and the metal wiring process is completed.

In the above-described conventional MUGROM manufacturing method, since the first polycrystalline silicon gate electrode layer 13 is formed after the first cell ion implantation process, the first polycrystalline silicon gate electrode layer 13c is missed in the first cell ion implantation region 20a. It will be aligned. Therefore, in consideration of such misalignment, the cell ion implantation mask has to be made larger than the actual cell channel region, thereby limiting the channel length of the cell. In addition, in case of severe misalignment, the entire bit line does not operate in the cell array configuration. This lowers the yield. As cell density increases, the cell area decreases and the tolerance of misalignment increases relative to the cell area.

Therefore, since the cell area must be made larger than necessary, the high density of the memory cell is reduced, and it is a factor that hinders the large capacity of the ROM.

Accordingly, an object of the present invention is a self-aligned ion implantation method capable of eliminating misalignment between a cell ion implantation region and a gate electrode layer in a semiconductor device having a multi-gate MOS transistor structure in order to solve the problems of the prior art as described above. To provide.

Another object of the present invention is to provide a self-aligned ion implantation method capable of improving the density of MUGROM and increasing the production yield.

In order to achieve the above object, the method of the present invention provides a multi-gate type in which a plurality of first gate electrode layers and second gate electrode layers are electrically insulated and alternately arranged on a channel region between a drain region and a source region of a semiconductor substrate. In a method of manufacturing a semiconductor device having a MOS transistor structure, first, a first gate electrode layer is formed, and impurity ions are implanted to self-align with a first gate electrode layer adjacent to a predetermined channel region between the first gate electrode layers. do. Thereafter, a second gate electrode layer is formed between the first gate electrode layers, and the edges of the second gate electrode layer cover the edges of the adjacent first gate electrode layers. Impurity ions are implanted to self-align with the second gate electrode layer adjacent to the predetermined channel region under the first gate electrode layer. The predetermined channel region under the gate electrode layers becomes a depletion channel region and the other channel region is maintained as an incremental channel region.

The present invention will be described in detail with reference to the accompanying drawings.

5a to d are views showing the procedure of cell ion implantation of MUGROM according to an embodiment of the present invention.

In FIG. 5A, the field oxide layer is thermally grown to define an active region after the impurity for controlling the field threshold voltage is implanted into the cell isolation region of the P-type (<100> direction) silicon subsurface 10. Thereafter, a process of implanting P-type impurities in order to grow the first gate oxide film 12 and to adjust the threshold voltage of the active region to 0.7V before or after the growth of the first gate oxide film 12 is shown.

In FIG. 5B, after the process is completed, the first polycrystalline silicon layer is formed on the entire surface of the resultant, and the first polycrystalline silicon layer is etched by applying the first gate mask to form the first gate electrode layer 13. Subsequently, a first cell ion implantation mask 11 is formed to cover the channel region except for the first channel region 20b (the region for forming the depletion channel region). The first cell ion implantation mask is formed. The first channel region 20b having the shape of self-aligning with the first gate electrode layer 13 by ion-implanting an N-type impurity into the predetermined first channel region 20b using (11). (The same reference numerals are used as the same region as the predetermined first channel region).

In this case, the first channel region 20b is self-aligned with the first gate electrode layer because the N-type impurity is implanted at an injection energy enough to penetrate only the first gate oxide layer 12. Impurities that are injected into the cell ion implantation mask 11 and the first gate electrode layer 13 do not reach the silicon substrate 10, and as a result, only impurities that are injected into the surface of the first gate oxide film 12 that are exposed to the surface may be removed. This is because the silicon substrate is reached. In this case, the polycrystalline silicon is used as the material constituting the gate electrode layer because the polycrystalline silicon is a high melting point metal which does not melt even in a high temperature heat treatment process and maintains its shape.

In general, the impurity must be implanted with a predetermined implantation energy for impurity implantation, and a phenomenon in which the gate electrode layer used as the ion implantation mask is melted by the thermal energy prevents the ion implantation process from being reliably performed. Since the polysilicon is a high melting point metal that can maintain its shape even in thermal energy supplied during ion implantation, when polycrystalline silicon is used as a material of the gate electrode layer, self-aligned ion implantation using the gate electrode layer as an ion implantation mask Can be effectively implemented.

In addition, since the first cell ion implantation mask 11 only needs to prevent the N-type impurities from being injected into the channel region other than the first channel region 20b, the first cell ion implantation mask 11 The process margin can be increased because no fine photo-etching process is required (the edge of the first cell ion implantation mask is largely aligned with one edge of the first gate electrode layer (the direction in which the first channel region is to be formed). It is free to vary the size of the first cell ion implantation mask by the width of the first gate electrode layer because it can be formed or shaped to coincide with the other edge (the direction opposite to the direction in which the first channel region is to be formed). Therefore, the problem of deterioration in reliability of the semiconductor device due to misalignment, which is a problem in the conventional method, can be reduced.

In FIG. 5C, the second polycrystalline silicon layer is deposited after removing the first cell ion implantation mask 11 and growing the second gate oxide layer 15. The second polycrystalline silicon is etched by applying the second gate mask to leave the second gate electrode layer 16. The second gate electrode layer 16 is formed between the first gate electrode layer 13 and covers the edge of the first gate electrode layer 13 adjacent to the edge of the second gate electrode layer 16. At this time, it can be seen from FIG. 5C that the second gate electrode layer 16a is formed on the same vertical line as the first channel region 20b formed below. Thereafter, a second cell ion implantation mask 14 is formed to cover the channel region except for the predetermined second channel region 20a (the region for forming the depletion channel region), and the second cell ion implantation mask 14 is formed. The N-type impurity is ion-implanted through the first gate electrode layer 13c into the second second channel region 20a under the first gate electrode layer 13c by applying a mask to the second channel region 20a ( The same reference numerals as the same region as the second predetermined channel region) are formed. In this case, the N-type impurity is formed to be self-aligned with the second gate electrode layers 16b and 16c adjacent to the first gate electrode layer 13c, by the same principle as described with reference to FIG. 5b. That is, since the N-type impurity implanted to form the second channel region 20a is implanted with an implantation energy sufficient to penetrate only the first gate electrode layer 13c, the second cell ion implantation mask, and the The overlapping portion of the edge portion of the first gate electrode layer and the edge portion of the second gate electrode layer is not perforated.

FIG. 5D illustrates a state in which the metallization process is completed after covering the first interlayer insulating film 17 and the second interlayer insulating film 18 after the self-aligned ion implantation is completed.

According to an embodiment of the present invention, since each of the first channel region and the second channel region is formed to be self-aligned with the first gate electrode layer and the second gate electrode layer, problems caused by misalignment can be solved. Since the threshold voltage is controlled by doping impurities of the same type as the semiconductor substrate on the entire surface of the semiconductor substrate before the first gate electrode layer is formed, it is possible to satisfy the requirements of the incremental transistor requiring a uniform threshold voltage, thereby providing reliability and electrical reliability of the semiconductor device. Improved properties.

6a to d are views showing the procedure of cell ion implantation of MUGROM according to another embodiment of the present invention.

In FIG. 6A, the field oxide layer is thermally grown after the impurity for controlling the field threshold voltage is injected into the cell isolation region of the P-type (<100> direction) silicon substrate 10, and the active region is defined. The state in which the N-type impurity is ion-implanted into the channel region 20 so as to be a depletion channel region (the threshold voltage is negative) is shown.

In FIG. 6B, after the process is finished, the first gate oxide layer 12 is grown and the first polycrystalline silicon layer is deposited before and after the first polycrystalline silicon layer is selectively etched by applying the first gate mask. 13) is shown.

In FIG. 6C, after the process is completed, the second gate oxide film 15 is grown and the second polysilicon layer is deposited. A second gate electrode layer 16 is formed by selectively etching the polysilicon layer by applying a second gate mask. Subsequently, a cell ion implantation mask 19 is applied to the bottom of the gate electrode layers 13a, 13b, 16b, 16c except for the gate electrode layers 13c, 16a, which will eventually become a depletion channel region. P-type impurities are implanted into the predetermined channel region through the gate electrode layers 13a, 13b, 16b, and 16c. Therefore, the channel region 21 into which the P-type impurity is implanted is changed from the depletion channel region to the incremental channel region, and only the predetermined channel region 20 under the gate electrode layers 13c and 16a is depleted. Will remain the same. In this case, the channel region 20 is formed to be self-aligned with the gate electrode layers 13c and 16a, and the formation principle thereof is the same as described with reference to FIGS. 5b and c.

In FIG. 6D, after the self-aligned ion implantation is completed, the first intermediate insulating film 17 and the second intermediate insulating film 18 are covered and the metal wiring process is completed.

As described above, in the present invention, the gate electrode layer is used as a self-alignment mask during the cell ion implantation, thereby preventing misalignment between the gate electrode layer and the ion implantation region. Therefore, since the cell area does not have to be made larger than necessary, the density of memory cells can be increased.

In the embodiment of the present invention, the gate electrode layer uses polycrystalline silicon, but a material having the same conductivity or higher as that of the polycrystalline silicon, such as silicide of a high melting point metal or a high melting point metal body, may be used. In addition, the present invention is not limited to the manufacturing method of MUGROM, but has a multi-gate MOS transistor structure, and can be applied to all manufacturing methods of semiconductor devices for selectively adjusting the gate threshold voltage thereof.

Claims (4)

Fabrication of a semiconductor device having a multi-gate MOS transistor O structure in which a plurality of first gate electrode layers and second gate electrode layers are alternately electrically insulated from each other on a channel region between a drain region and a source region of a semiconductor substrate. The method includes implanting impurities of a different conductivity type from the substrate into the channel region, and forming a plurality of first gate electrode layers at predetermined intervals so as to be insulated from the substrate and electrically insulated from the substrate on the channel region. A plurality of second gate electrode layers are formed on the channel region between the first gate electrode layers so as to be electrically insulated from the substrate and the first gate electrode layer, and the edges of the second gate electrode layers cover the edges of the adjacent first gate electrode layers. A depletion type of the channel region under the gate electrode layers By selectively ion implanting impurities of the same conductivity type as the substrate through the gate electrode layer in the remaining channel regions except for the channel region where the region is to be formed, thereby self-aligning by adjacent gate electrode layers. A self-aligned ion implantation method of a semiconductor device having a multi-gate MOS transistor structure, wherein the ion implanted impurities can be left only in a channel region where an increased channel region under the gate electrode layer is to be formed. The method of claim 1, wherein the substrate is of P type, and the impurity implanted into the channel region is of N type. The method of claim 1, wherein the substrate is N-type, and the impurity implanted into the channel region is P-type. 4. The self-alignment of a semi-element having a multi-gate MOS transistor structure according to claim 1, 2 or 3, wherein the first gate electrode layer and the second gate electrode layer are formed of polycrystalline silicon. Ion implantation method.