KR920007188B1 - Lithographic process of electric beam - Google Patents
Lithographic process of electric beam Download PDFInfo
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- KR920007188B1 KR920007188B1 KR1019890020708A KR890020708A KR920007188B1 KR 920007188 B1 KR920007188 B1 KR 920007188B1 KR 1019890020708 A KR1019890020708 A KR 1019890020708A KR 890020708 A KR890020708 A KR 890020708A KR 920007188 B1 KR920007188 B1 KR 920007188B1
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 239000010408 film Substances 0.000 claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 238000010894 electron beam technology Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000609 electron-beam lithography Methods 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 4
- 238000001459 lithography Methods 0.000 abstract description 6
- 238000004528 spin coating Methods 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
제1도는 종래 전자 빔 리소그래피를 위한 다층 레지스트막의 구성을 도시한 단면도.1 is a cross-sectional view showing the configuration of a multilayer resist film for conventional electron beam lithography.
제2도는 본 발명에 의한 전자 빔 리소그래피를 위한 다층 레지스트막의 구성을 도시한 단면도.2 is a cross-sectional view showing the configuration of a multilayer resist film for electron beam lithography according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
PR1 : 제1포토레지스트 PR2 : 제2포토레지스트PR1: first photoresist PR2: second photoresist
M : 금속박막 1 : 절연막M: metal thin film 1: insulating film
본 발명은 리소그래피 공정에 관한 것으로, 특히 전자 빔 리소그래피(Electron Beam Lithography)공정에 관한 것이다.FIELD OF THE INVENTION The present invention relates to lithographic processes, and more particularly to electron beam lithography processes.
마이컴의 출현과 더불어 OA(Office Automation)기기를 비롯한 이른바 정보기기 그리고 민생용품에 이르기까지 널리 사용되고 있는 반도체 소자들은, 미세 가공기술·회로기술등의 진보에 따라 대용량화, 고집적화의 소자 개발이 진척되고 있으며, 이러한 반도체 소자를 제작함에는 실리콘 웨이퍼의 제작에서부터 집적회로의 패키지를 봉하여 출하에 이르기까지 여러단계의 제조공정이 필요하다. 반도체 제조공정중에서도, 반도체 소자를 제조할 때에 그 구조를 결정하는 프로세스에 사용되는 리소그래피 공정은 반도체 소자의 고집적화에 따라 점점 그 중요성이 높아지고 있다. 리소그래피는 소자의 패턴 정보를 웨이퍼 상에 정확히 전달하는 기술로, 웨이퍼 표면에 도포한 레지스트상에 패턴 데이터대로 노광하고 현상등의 레지스트 프로세스를 행하여 패턴을 형성하는 것이다.With the advent of microcomputers, semiconductor devices, which are widely used in OA (Office Automation) devices, so-called information devices, and consumer products, are being developed with the development of devices of high capacity and high integration in accordance with advances in fine processing technology and circuit technology. In order to manufacture such a semiconductor device, a manufacturing process of several stages is required, from fabrication of a silicon wafer to sealing and shipping a package of an integrated circuit. In the semiconductor manufacturing process, the lithography process used for the process of determining the structure at the time of manufacturing a semiconductor element becomes increasingly important with the high integration of a semiconductor element. Lithography is a technique for accurately transferring the pattern information of an element onto a wafer. The pattern is exposed by pattern data on a resist coated on the wafer surface and subjected to a resist process such as development to form a pattern.
이러한 리소그래피의 주류는 가시광을 사용하는 이른바 포토 리소그래피이다. 그러나, 광을 사용한 리소그래피 수단에서는 회절현상 때문에 광파장 이하의 미세 패턴 형성은 곤란하게 되고, 그 한계를 타파하기 위하여, 단파장 자외선을 사용하는 리소그래피, 전자 빔 리소그래피, X선 리소그래피, 이온 빔 리소그래피 등의 여러방법이 시도되어 왔다. 또 레지스트 프로세스의 면에서도 다층 레지스트 프로세스, 콘트라스트 인 헨스먼트 리소그래피, 드라이 현상등의 검토가 진행되어 왔다.The mainstream of such lithography is so-called photolithography using visible light. However, in the lithography means using light, it is difficult to form sub-wavelength fine patterns due to diffraction phenomenon. The method has been tried. In terms of the resist process, a multilayer resist process, contrast enhancement lithography, dry development, and the like have been studied.
전자 빔 리소그래피는 마스크 기판 흑은 웨이퍼상에 도포한 레지스트에 5∼50keV의 고속 전자 빔을 조사하고, 조사한 부분의 레지스트의 화학반응을 이용하여 원하는 패턴을 형성하는 노광기술이다.Electron beam lithography is an exposure technique in which a mask substrate black is irradiated with a high-speed electron beam of 5 to 50 keV onto a resist coated on a wafer, and a desired pattern is formed by using a chemical reaction of the resist of the irradiated portion.
제1도는 종래 전자 빔 리소그래피를 위한 다층 레지스트막의 구성을 도시한 단면도이다.1 is a cross-sectional view showing the configuration of a multilayer resist film for conventional electron beam lithography.
먼저, 소정의 패턴을 형성하기 위한 구조물상에 노광 표면을 평탄화하기 위한 평탄화층 예컨대 제1포토 레지스트(PR1)를 스핀코팅(spin coating)하고, 이 제1포토레지스트(PR1)위에 보호층인 절연막(I)을 스핀 코팅하며, 이 절연막(I)위에 포토레지스트의 패턴이 형성되는 제2포토레지스트(PR2)를 스핀코팅한다. 그리고, 전자 빔 조사시 상기 제2포토레지스트(PR2)에서 손실되는 전자를 채우기 위한 금속박막(M) 예컨대 알루미늄 혹은 금을, 진공증착 혹은 스퍼터(sputter) 장치를 사용하여 상기 제2포토레지스트상에 형성함으로써 다층 레지스트막을 구성한다. 그리고 원하는 부분에 전자 빔을 조사하여 상기 구조물상에 소정의 패턴을 형성한다.First, a spin coating of a planarization layer, for example, a first photoresist PR1, to planarize an exposure surface on a structure for forming a predetermined pattern, and an insulating film as a protective layer on the first photoresist PR1 (I) is spin-coated, and the second photoresist (PR2) on which the pattern of photoresist is formed is formed on the insulating film (I). In addition, a metal thin film M such as aluminum or gold for filling electrons lost from the second photoresist PR2 upon electron beam irradiation is deposited on the second photoresist using a vacuum deposition or sputtering device. By forming, a multilayer resist film is comprised. The electron beam is irradiated to a desired portion to form a predetermined pattern on the structure.
이와 같은 종래 전자 빔 리소그래피를 위한 다층 레지스트막은, 전자 빔 노광시 원하는 패턴이 형성되는 제2포토레지스트위에 금속박막이 형성되어 있으므로, 상기 노광후 현상공정에서 두 물질을 제거하기가 어렵다. 즉 금속박막을 제거하기 위해서는 산을 사용하여야 하고, 포토레지스트의 현상액은 알칼리성이기 때문에 두 용액의 반응을 조절하기가 어려워 안정된 공정이 곤란하다. 또한, 상기 금속박막 형성시에 사용되는 장치에 오염이 많이 되고, 금속이 포토레지스트 속으로 파고 들어 이 포토레지스트의 제거가 어려워진다.In the conventional multilayer resist film for electron beam lithography, since the metal thin film is formed on the second photoresist in which the desired pattern is formed during the electron beam exposure, it is difficult to remove both materials in the post-exposure developing process. That is, an acid must be used to remove the metal thin film, and since the developer of the photoresist is alkaline, it is difficult to control the reaction of the two solutions, and thus, a stable process is difficult. In addition, the apparatus used for forming the metal thin film is highly contaminated, and the metal penetrates into the photoresist, making it difficult to remove the photoresist.
따라서 본 발명의 목적은 상기한 종래 기술의 문제점을 해결하기 위하여 전자 빔 리소그래피의 현상공정을 안정하게 할 수 있는 전자 빔 리소그래피 공정을 제공하는데 있다.Accordingly, an object of the present invention is to provide an electron beam lithography process that can stabilize the developing process of electron beam lithography in order to solve the above problems of the prior art.
상기의 목적을 달성하기 위하여 본 발명의 공정은, 다층 레지스트막을 사용하는 전자 빔 리소그래피 공정에 있어서, 상기 다층 레지스트막은 평탄화층인 제1포토레지스트와, 보호층인 절연막, 전자 빔 조사시 손실되는 전자를 채우기 위한 금속박막, 그리고 식각공정을 위한 포토레지스트 패턴이 형성되는 제2포토레지스트가 차례로 적층되어 형성됨을 특징으로 한다.In order to achieve the above object, the process of the present invention is an electron beam lithography process using a multilayer resist film, wherein the multilayer resist film is a first photoresist as a planarization layer, an insulating film as a protective layer, and electrons lost upon irradiation with an electron beam. The metal thin film for filling the gap, and the second photoresist for forming the photoresist pattern for the etching process are sequentially stacked.
이하, 첨부된 도면을 참조하여 본 발명을 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.
제2도는 본 발명에 의한 전자 빔 리소그래피를 위한 다층 레지스트막의 구성을 도시한 단면도이다.2 is a cross-sectional view showing the configuration of a multilayer resist film for electron beam lithography according to the present invention.
먼저, 소정의 패턴을 형성하기 위한 구조물상에 노광 표면을 평탄화하기 위한 평탄화층 예컨대 제1포토 레지스트(PR1)를 스핀코팅하고, 이 제1포토레지스트(PR1)위에 보호층인 절연막(I)을 스핀코팅하며, 전자 빔 조사시 손실되는 전자를 채우기 위한 금속박막(M) 예컨대 알루미늄 혹은 금을, 진공증착 혹은 스퍼터 장치를 사용하여 상기 절연막(I)상에 형성하고, 이 절연막상에 식각공정을 위한 포토레지스트 패턴이 형성 되는 제2포토레지스트를 스핀코팅함으로써 다층 레지스트막을 구성한다. 그리고 원하는 부분에 전자 빔을 조사하여 상기 구조물상에 소정의 패턴을 형성한다.First, by spin coating a planarization layer, for example, a first photoresist PR1, to planarize an exposure surface on a structure for forming a predetermined pattern, and insulating film I as a protective layer on the first photoresist PR1. A metal thin film (M) such as aluminum or gold, which is spin coated and filled with electrons lost during electron beam irradiation, is formed on the insulating film (I) using a vacuum deposition or sputtering device, and an etching process is performed on the insulating film. The multi-layer resist film is formed by spin coating a second photoresist on which a photoresist pattern is formed. The electron beam is irradiated to a desired portion to form a predetermined pattern on the structure.
이상과 같이 본 발명의 전자 빔 리소그래피 공정에 사용되는 다층 레지스트막은 제2포토레지스트 아래에 금속박막을 형성함으로써, 전자 빔 조사 즉 노광 공정후 현상공정시 상기 제2포토레지스트의 제거가 금속 박막에 의해 영향을 받지 않고 진행되기 때문에 공정의 개발 유지가 쉽다. 또한, 금속박막 형성장치의 오염이 작고, 상기 제2포토레지스트의 제거가 쉽다.As described above, in the multilayer resist film used in the electron beam lithography process of the present invention, a metal thin film is formed under the second photoresist, so that the removal of the second photoresist is performed by the metal thin film during the electron beam irradiation, that is, the development process after the exposure process. It is easy to maintain the development of the process because it proceeds unaffected. In addition, the contamination of the metal thin film forming apparatus is small, and the removal of the second photoresist is easy.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890020708A KR920007188B1 (en) | 1989-12-30 | 1989-12-30 | Lithographic process of electric beam |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890020708A KR920007188B1 (en) | 1989-12-30 | 1989-12-30 | Lithographic process of electric beam |
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| Publication Number | Publication Date |
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| KR910013490A KR910013490A (en) | 1991-08-08 |
| KR920007188B1 true KR920007188B1 (en) | 1992-08-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019890020708A KR920007188B1 (en) | 1989-12-30 | 1989-12-30 | Lithographic process of electric beam |
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| KR (1) | KR920007188B1 (en) |
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