KR920007167A - SRAM with high load resistor and its manufacturing method - Google Patents

SRAM with high load resistor and its manufacturing method Download PDF

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KR920007167A
KR920007167A KR1019900015451A KR900015451A KR920007167A KR 920007167 A KR920007167 A KR 920007167A KR 1019900015451 A KR1019900015451 A KR 1019900015451A KR 900015451 A KR900015451 A KR 900015451A KR 920007167 A KR920007167 A KR 920007167A
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South Korea
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insulating layer
layer
pattern
forming
insulating
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KR1019900015451A
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Korean (ko)
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KR940000312B1 (en
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윤대원
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정몽헌
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

고부하 저항체를 갖는 SRAM 및 그 제조방법SRAM with high load resistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명에 의해 부하저항체를 형성하기 위하여 콘택패드 마스크, 절연막 마스크, 콘택마스크, 필라멘트 마스크를 배열한 레이 아웃트 도면,5 is a layout view in which a contact pad mask, an insulating film mask, a contact mask, and a filament mask are arranged to form a load resistor according to the present invention;

제6A도 내지 제6F도는 제5도의 A-A'단면의 부하저항체를 제조하는 단계를 나타낸 단면도.6A to 6F are cross-sectional views showing a step of manufacturing a load resistor of A-A 'cross-section of FIG.

Claims (8)

반도체 기판 소정상부에 MOSFET의 Q1 내지 Q4가 각가 형성되되, Q1 및 Q4의 드레인은 Q3의 게이트에 접속되고, Q2 및 Q3의 드레인은 Q4의 게이트에 접속되고, Q1 및 Q2의 소오스는 각각 Bit라인 및 Bit 라인에 접속되고, Q2 및 Q3의 소오스는 Vss 배선에 접속되어 이루어진 구조 상부에 절연층이 형성되고, 이 절연층 상부에는 상기 Q1 및 Q4의 드레인과 Q2 및 Q3의 드레인의 각각에 접속된 콘택패드와 Vcc배선이 형성되고, 그 상부에서 사기 콘택패드에서 두개 부하정항체(R1 및 R2)각각의 한단자가 접속되고, 부하저항체의 다른 단자는 Vcc배선에 접속된 구조로 이루어지는 SRAM에 있어서, 상기 콘택패드 및 Vcc배선을 포함하는 전체구조 상부에 형성된 절연층과, 상기 절연층 상부에 형성된 제1절연막 패턴 및 제2절연막 패턴과, 상기 제1절연막 패턴 측면의 가장자리를 따라 소정폭과 소정길이를 갖도록 형성된 캐비티(cavity)에 부하저항체용 폴리실콘층의 형성된 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.Q1 to Q4 of the MOSFET are formed on the semiconductor substrate, the drains of Q1 and Q4 are connected to the gate of Q3, the drains of Q2 and Q3 are connected to the gate of Q4, and the sources of Q1 and Q2 are respectively Bit lines. And an insulating layer is formed on an upper portion of the structure connected to the bit line, and the source of Q2 and Q3 is connected to the Vss wiring. In a SRAM having a structure in which a contact pad and a Vcc wiring are formed, and at the top thereof, one terminal of each of the two load positive antibodies R1 and R2 is connected, and the other terminal of the load resistor is connected to the Vcc wiring. An insulating layer formed on the entire structure including the contact pad and the Vcc wiring, a first insulating pattern and a second insulating pattern formed on the insulating layer, and predetermined edges along side edges of the first insulating pattern SRAM having a high load resistor, characterized in that the polysilicon layer for the load resistor is formed in a cavity formed to have a width and a predetermined length. 제1항에 있어서, 상기 캐비티 내부에만 형성된 폴리실리콘에는 고저항 갖도록 불순물이 예정된 농도로 도프된 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.The SRAM having a high load resistor according to claim 1, wherein the polysilicon formed only in the cavity is doped with a predetermined concentration so that the polysilicon has a high resistance. 상기 제1항에 있어서, 상기 제1절연막 패턴 및 제2절연막 패턴에서, 상기 제1절연막은 산화막이고 제2절연막은 질화막인 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.The SRAM according to claim 1, wherein in the first insulating pattern and the second insulating pattern, the first insulating layer is an oxide layer and the second insulating layer is a nitride layer. 상기 제1항에 있어서, 상기 제1절연막 패턴 및 제2절연막 패턴에서, 상기 제1절연막은 산화막이고 제2절연막은 산호막인 것을 포함하는 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.The SRAM according to claim 1, wherein in the first insulating pattern and the second insulating pattern, the first insulating layer is an oxide layer and the second insulating layer is a coral layer. 실리콘 기판 상부에 필드산화막을 선택적으로 제거하여 엑티브 영역을 형성하는 단계와, 예정된 영역에 게이트선을 형성하고, 소오스 및 드레인을 형성하여 MOSFET의 Q1 내지Q4를 형성하는 단계와, 상기 Q1 내지 Q4상부에 절연층을 형성하고 부하저항기가 접속되는 Q1 내지 Q4의 드레인영역 상부에 콘택마스크를 이용하여 콘택홈을 형성하는 단계와, 상기 절연층과 콘택홈 상부에 도전층을 형성한 다음, 콘택패드 마스크 및 Vcc 배선마스크를 이용하여 콘택패드 및 Vcc배선을 형성하는 단계와, 상기 콘택패드 및 Vcc배선 상부에 절연층를 형성한다음 콘택패드 및 Vcc배선에 접속되는 부하저항체를 형성하는 단계로 이루어지는 SRAM 셀 제조방법에 있어서, 상기 부하저항체의 단면적의 선폭이 노광기줄에 의해 형성되는 선폭보다 극소화시키기 위하여, 상기 콘택패드 Vcc배선 상부의 절연층 상부에 제1절연막 및 제2절연막을 형성한 다음 그 상부에 감광막을 도포하는 공정과 상기 감광막을 소정부분 제거하여 감광마스크를 형성하고 비등방성 식각으로 제2절연막과 제1절연막을 소정부분 제거하여 제2절연막패턴 및 제1절연막 패턴을 형성하는 공정과, 상기 감광막 마스크를 제거한다음, 제1절연막 패턴의 가장자리를 등방성 식각으로 제1절연막 패턴의 가장자리의 소정폭이 제거된 캐비티를 형성하는 공정과, 상기 제2절연막 패턴 및 절연층 상부를 포함하는 전체구조에 폴리 실리콘층을 형성하고, 비등방성 식각공정으로 노출된 폴리실리콘층을 식각하여 제1절연막 패턴의 가장자리에 형성된 캐비티내에 폴리실리콘을 남기는 공정으로 이루어져 막대형태의 폴리실리콘 부하 저항체를 형성하는 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.Selectively removing the field oxide film on the silicon substrate to form an active region, forming a gate line in a predetermined region, forming a source and a drain to form Q1 to Q4 of the MOSFET, and forming the Q1 to Q4 upper portion Forming a contact layer using a contact mask on the drain region of Q1 to Q4 to which the load resistor is connected, and forming a conductive layer on the insulating layer and the contact groove, and then forming a contact pad mask. And forming a contact pad and Vcc wiring using a Vcc wiring mask, forming an insulating layer on the contact pad and the Vcc wiring, and then forming a load resistor connected to the contact pad and the Vcc wiring. In the method, in order to minimize the line width of the cross-sectional area of the load resistor than the line width formed by the exposure line, the contact pad Forming a first insulating film and a second insulating film on the insulating layer above the Vcc wiring and then applying a photoresist film on the upper part of the Vcc wiring; and removing a predetermined portion of the photoresist film to form a photoresist mask and anisotropically etching the second insulating film and the first Removing a predetermined portion of the insulating layer to form a second insulating layer pattern and a first insulating layer pattern, removing the photoresist mask, and then removing the predetermined width of the edge of the first insulating layer pattern by isotropic etching the edge of the first insulating layer pattern. Forming a cavity, and forming a polysilicon layer on the entire structure including the second insulating layer pattern and the upper part of the insulating layer, and etching the polysilicon layer exposed by an anisotropic etching process to form an edge of the first insulating layer pattern The process of leaving polysilicon in the cavity is formed to form a rod-shaped polysilicon load resistor SRAM having a load resistor. 제5항에 있어서, 상기 감광막 마스크를 제고한 다음, 제1절연막 일측면은 캐비티가 형성되지 않도록 필라멘트 마스크를 이용하여 제1절연막 패턴 및 제2절연막 패턴의 예정된 영역에 감광막을 형성한 다음 등방성 식각을 하여 그로 인하여 감광막이 있는 부분은 캐비티가 형성되지 못하도록 하는 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.The method of claim 5, wherein after the photoresist mask is removed, a photoresist layer is formed on predetermined regions of the first insulation pattern and the second insulation pattern using a filament mask so that one side of the first insulation layer is not formed with a cavity. SRAM having a high load resistor, characterized in that the portion with the photoresist thereby prevent the cavity is formed. 제5항에 있어서, 상기 제1절연막 패턴의 가장자리에 소정 폭이 제거된 캐비티를 형성하는 공정후에, 후에 형성될 부하저항체를 절연층 하부의 콘택패드와 Vcc배선에 접속하기 위하여, 콘택패드와 Vcc배선 소정상부 콘택홀을 형성한 다음, 폴리실리콘층을 형성하는 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.The contact pad and the Vcc according to claim 5, wherein after the step of forming a cavity having a predetermined width removed from an edge of the first insulating film pattern, a load resistor to be formed later is connected to a contact pad and a Vcc wiring under the insulating layer. And a polysilicon layer after forming a contact upper portion of the wiring predetermined upper portion and forming a contact hole. 제5항에 있어서, 상기 제2절연막 패턴 및 절연층 상부에 폴리실리콘층을 형성한후에 폴리실리콘층의 저항을 크게하기 위하여, 예정된 불순물을 소정의 농도로 폴리실리콘층에 이온주입시키는 것을 특징으로 하는 고부하 저항체를 갖는 SRAM.The polysilicon layer is ion implanted into the polysilicon layer at a predetermined concentration to increase the resistance of the polysilicon layer after the polysilicon layer is formed on the second insulating layer pattern and the insulating layer. SRAM with high load resistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900015451A 1990-09-28 1990-09-28 Sram having a resistance resistor and fabricating method thereof KR940000312B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900015451A KR940000312B1 (en) 1990-09-28 1990-09-28 Sram having a resistance resistor and fabricating method thereof

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Application Number Priority Date Filing Date Title
KR1019900015451A KR940000312B1 (en) 1990-09-28 1990-09-28 Sram having a resistance resistor and fabricating method thereof

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KR920007167A true KR920007167A (en) 1992-04-28
KR940000312B1 KR940000312B1 (en) 1994-01-14

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