KR920007137A - Multiprobing test method of CMOS memory device - Google Patents

Multiprobing test method of CMOS memory device Download PDF

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Publication number
KR920007137A
KR920007137A KR1019900014491A KR900014491A KR920007137A KR 920007137 A KR920007137 A KR 920007137A KR 1019900014491 A KR1019900014491 A KR 1019900014491A KR 900014491 A KR900014491 A KR 900014491A KR 920007137 A KR920007137 A KR 920007137A
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KR
South Korea
Prior art keywords
test
cmos memory
memory device
probing
test method
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KR1019900014491A
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Korean (ko)
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KR930010725B1 (en
Inventor
강동만
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문정환
금성일렉트론 주식회사
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Priority to KR1019900014491A priority Critical patent/KR930010725B1/en
Publication of KR920007137A publication Critical patent/KR920007137A/en
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Publication of KR930010725B1 publication Critical patent/KR930010725B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

내용 없음No content

Description

시모스 메모리 소자의 멀티프로빙 시험방법Multiprobing test method of CMOS memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 8멀티 프로빙 EDS시험블록도.Figure 3 is an eight multi probing EDS test block diagram of the present invention.

제4도는 제3도의 상세 회로도.4 is a detailed circuit diagram of FIG.

제5도는 본 발명의 시험 순서도.5 is a test flow chart of the present invention.

Claims (3)

VBB제너레이터 회로가 내장된 시모스 메모리 소장의 멀티프로빙 시험시 내부 VBB전압과 외부 VBB전압을 이용하여 EDS시험하는 시모스 메모리 소자의 멀티 프로빙 시험방법.A multi-probing test method for CMOS memory devices in which EDS tests are performed using an internal V BB voltage and an external V BB voltage in a multi-probing test of a CMOS memory device having a V BB generator circuit. 제1항에 있어서, 침내부 VBB를 측정하여 VBB불량칩이 발견되는 스테이션의 피시험 웨이퍼에만 제한적으로 외부 VBB를 인가하고 EDS시험하는 시모스 메모리 소자의 멀티 프로빙 시험 방법.The method of claim 1, wherein the needle inside the measured V BB by applying an external V BB limited only to the wafer under test of the station is detected V BB bad chip, and multi-probing of the CMOS memory device of EDS test Test method. 제1항에 있어서, 외부 VBB셀팅조건을 VCC에 관계없이 일정하게 하거나 또는 VCC조건에서 따른 전압으로 리세트하면서 EDS시험하는 멀티 프로빙 시험방법.The method of claim 1, wherein the multi-probing testing method for EDS test and reset according to a voltage at a constant or V CC conditions regardless of the outer conditions and selting V BB V CC. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900014491A 1990-09-13 1990-09-13 Multi-probing testing apparatus of c-mos memory KR930010725B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900014491A KR930010725B1 (en) 1990-09-13 1990-09-13 Multi-probing testing apparatus of c-mos memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900014491A KR930010725B1 (en) 1990-09-13 1990-09-13 Multi-probing testing apparatus of c-mos memory

Publications (2)

Publication Number Publication Date
KR920007137A true KR920007137A (en) 1992-04-28
KR930010725B1 KR930010725B1 (en) 1993-11-08

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KR1019900014491A KR930010725B1 (en) 1990-09-13 1990-09-13 Multi-probing testing apparatus of c-mos memory

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100591757B1 (en) 2003-09-02 2006-06-22 삼성전자주식회사 EDS inspection system

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KR930010725B1 (en) 1993-11-08

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