KR920006878Y1 - Auto-vertical centering circuit - Google Patents

Abstract

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Description

Automatic vertical centering circuit

1 is a conventional vertical centering circuit diagram.

FIG. 2A is a timing chart of a general monitor, and a screen state display diagram according to the timing chart of FIG. 2A of FIG. 2B.

3 is an automatic vertical centering circuit diagram according to the present invention.

4A is a timing chart when the front porch is smaller than the back porch, and FIG. 4B is a screen state display diagram according to the timing chart of FIG.

FIG. 5A is a timing chart when the front porch is larger than the back porch, and FIG. 5B is a screen state display diagram according to the timing chart of FIG.

* Explanation of symbols for main parts of the drawings

1: Voltage division circuit 2: Vertical IC

3: Mode discrimination circuit R ₁ to R ₁₃ : Resistance

VR ₁ : Variable resistor Q ₁ ~ Q ₄ : Transistor

V. DY: Vertical deflection coil C ₁ ~ C ₄ : Condenser

The present invention relates to vertical centering, and more particularly, to an automatic image vertical centering circuit of a multiple synchronization monitor which automatically matches the vertical position of an image regardless of a mode in a multiple synchronization monitor.

In the conventional vertical centering circuit, as shown in FIG. ₁ , a voltage dividing circuit 1 for dividing a DC power supply voltage B ⁺ by connecting a resistor R ₁ , a variable resistor VR ₁ , and a resistor R ₂ in series is shown. The output of is simultaneously applied to the bases of the transistors Q ₁ and Q ₂ (point A). The transistors Q ₁ and Q ₂ are complementary symmetrical connections and the collector of transistors Q ₁ is a DC power supply (B ⁺ ), The collector of transistor (Q ₂ ) is grounded, and the emitters of transistors (Q ₁ , Q ₂ ) are connected to each other (point B), grounded through capacitor (C ₁ ) and through resistor (R ₃ ). Condenser (C ₂ ) resistors (R ₅ , R ₆ ) and vertical deflection coils (V, DY) are simultaneously connected (C point) and the vertical deflection coil (V, DY) and the other side of resistor (R ₅ ) are connected. It is connected to the vertical deflection output terminal (OUT) of the vertical IC (2) and is grounded through the series connection of the capacitor (C ₄ ) resistor (R ₇ ), and the other side of the capacitor (C ₂ ) is connected to the resistor (R ₈ , R _9). At the same time, the ground is connected via a resistor (R ₄ ) and the resistor (R ₈ ) is connected to the capacitor (G) connected to the resistor (R ₈ ) and the other side of the resistor (R ₉ ) to connect the vertical IC ( This is connected to the vertical deflection feedback terminal (F · B) of 2).

Referring to the operation of the configuration circuit, the divided voltage of the DC power supply B ⁺ is applied to the bases of the transistors Q ₁ and Q _{2 as} the variable resistor VR ₁ of the voltage dividing circuit 1 is varied. Is approved. At this time, the two transistors Q ₁ and Q ₂ operate in a complementary manner. When the transistor Q ₁ is 'on', the transistor Q ₂ is 'off' and when the transistor Q ₂ is 'on', the transistor Q _1. ) Is off. If the variable resistor VR ₁ is changed to increase the point A potential, the transistor Q ₁ will be 'on'. Therefore, the potential of the point B becomes high, and a current flows in the direction of ① to the resistor R ₃ , whereby the DC level of the vertical deflection coil V · DY rises.

Therefore, the vertical position of the screen is biased downward.

On the contrary, if the variable resistance VR ₁ is changed to lower the point A potential, the transistor Q ₂ will be 'on' and the point B potential will be lowered. Therefore, a current flows in the direction of the resistor R ₃ to decrease the DC level of the vertical deflection coil V · DY, and the vertical position of the screen is shifted upward.

The degree of vertical change of the screen is proportional to the potential change of the point A when the variable resistor VR ₁ is varied. In other words, if the point A potential is a little high, the screen will be slightly down, and if the variable resistance VR ₁ is adjusted so that the point A is too high, the screen will be much down.

However, a conventional vertical centering circuit as the monitor when a single-mode one can be applied without any problem multiple synchronization monitor when each time change the mode, so values and the vertical position of the screen biased up or down each time a variable resistor (VR ₁ ), And the vertical position of the screen should be adjusted to the center, which causes considerable inconvenience in use. This is the back porch front in the timing chart for each mode (Fig. 2 (a)). This is because the pores are different (A: blanking period, B: front porch, C: sync pulse width, D: back porch, E: display period, F: total period) in FIG. On the timing chart of FIG. 2 (a), if it is related to the vertical synchronization signal, it can be described as FIG. Is the front porch). Here, the back porch is the period from the end of the synchronization signal until the video signal appears. The back porch is the period from the top of the raster to the top of the video signal. The front porch is the end of the video signal. The period from the viewpoint to the start point of the synchronization signal means the period from the bottom of the video signal to the bottom of the raster on the screen.

The present invention has been made to solve the inconvenience in the conventional circuit described in detail with reference to the accompanying drawings as follows.

First, as shown in FIG. 3, the resistor R ₁ , the variable resistor VR ₁ , and the resistor R ₂ are connected in series and are connected between the DC power supply B ⁺ and the ground terminal to divide the DC voltage to divide the variable resistor. The output of the voltage division circuit 1 output through the intermediate terminal of VR ₁ is simultaneously applied to the bases of the transistors Q ₁ and Q ₂ that are complementary symmetrically connected (point A) and the collector of the transistor Q ₁ Connected to a DC power supply (B ⁺ ), the collector of transistor (Q ₂ ) is grounded, the emitters of transistors (Q ₁ , Q ₂ ) are connected (point B) and grounded through capacitor (C ₁ ) and resistor (R ₇₎ ) Is connected to the capacitor (C ₂ ) and the resistors (R ₉ , R ₁₀ ) and the vertical deflection coil (V · DY) in common (C point) and the vertical deflection coil (V · DY) and the resistor (R ₉ ). The other side is connected and connected to the vertical deflection output terminal (OUT) of the vertical IC (2) at the same time is grounded through the series connection of the capacitor (C ₃ ) resistor (R ₁₁ ) and the other side of the capacitor (C ₂ ) is connected to the resistor (R _8). Is connected to resistor (R ₁₂ ) and resistor (R ₁₃ ) at the same time, and resistor (R ₁₀ ) is connected to resistor (R ₁₃ ) and is connected to resistor (R ₁₂ ) through capacitor (C ₄ ). Connected to the vertical deflection feed-back terminal (F · B) of the vertical IC (2), and the voltage of the middle terminal (point A) of the voltage divider circuit 1 and the variable resistor VR _{1 is} connected through the resistor R ₅ . Connected to the collector of transistor Q ₃ , through resistor R ₆ to the emitter of transistor Q. the emitter of transistor Q ₃ is grounded, and the collector of transistor Q ₄ is connected to the B ⁺ voltage. The bases of the transistors Q ₃ and Q ₄ are connected to the mode determining circuit 3 through the resistors R ₃ and R ₄ , respectively.

Referring to the operation state of the configuration circuit, the transistor Q1 is 'on' when the variable point VR1 of the voltage dividing circuit 1 is turned and the transistor Q1 is 'on' and when the transistor Q1 is 'on', the point B potential Since the current in the direction of ① flows through the resistor R7, and the DC level of point C rises, it is biased downward to the vertical position of the screen. On the other hand, if the variable resistance VR1 is changed to decrease the point A potential, the transistor Since (Q2) is 'on' and the point B potential decreases accordingly, current flows in the direction (circle) in the resistor R7. Therefore, since the DC level at point C decreases, the vertical position of the screen is biased upward.

On the timing chart of the signal, when the front porch is smaller than the back porch as shown in Fig. 4 (a), and the front porch < back porch &quot; Connect the output of that mode to M1.

Therefore, the transistor Q3 is 'on', so the point A potential is lowered.

This is because current flows (current direction ③) to the collector-emitter of resistor R ₅ and transistor Q ₃ . When the A point potential is lowered, the B point potential is also lowered, and thus the vertical position of the screen is raised up by the downward bias, so that it is located at the center.

The mode discrimination circuit 3 is output when the front porch is larger than the back porch (front porch> back porch) as shown in FIG. 5 (a) on the timing chart of the signal (Fig. 5 (b)). Connect the output of that mode to M2. Thus, transistor Q ₄ is 'on' (current direction ④) and the point A potential is high. If the point A potential is described above, the point B potential also rises so that the vertical position of the screen is lowered as much as it is biased upward, so that it is positioned at the center (center).

By varying the potentiometer (VR ₁ ), you can change the screen vertically across all modes.

In this way, if the vertical position of the screen changes as the front porch and back porch are large and small in the multi-synchronous monitor, if the values of the resistors (R ₅ and R ₆ ) are properly selected, the screen returns to the center over all modes. There is no need to change the variable resistor VR _{1 at} every mode change. Here, the capacitor C ₁ is for removing ripple.

In the multi-synchronous monitor, the screen automatically enters the center in all modes without the need to adjust the screen vertical position every time the mode is changed, so it is convenient to use.

Claims (1)

Resistance (R ₁₎ and a variable resistor (VR ₁₎ resistance (R ₂₎ is series-connected direct current jeowon (B ⁺⁾ divided by the voltage divider circuit (1) to output through the intermediate terminal of variable resistor (VR1) for the A transistor receiving the output of the voltage dividing circuit 1 as a base and having a complementary symmetrical connection and whose emitter connection point is connected to the vertical deflection feedback terminal F · B of the vertical IC 2 through a resistor R ₇ ( In a known vertical centering circuit consisting of Q ₁ and Q ₂ , a mode discrimination circuit 3 for discriminating and outputting a mode in which the vertical position is biased and a mode discrimination signal from the mode discrimination circuit 3 are received. under the bias mode when the operation to adjust the output voltage of the voltage divider circuit (1) to the screen and the transistor (Q ₃₎ which is positioned in the center, receives a mode discrimination signal of the mode rocker arm circuit 3, the screen is the top bias It operates in the mode and adjusts the output voltage of the voltage division circuit (1). To automatically vertically centering circuit, characterized in that consisting of a transistor (Q ₄₎ of the screen to be positioned at the center.