KR920006791B1 - Circuit for independent synchronization eliminating the delay of reframing - Google Patents

Abstract

The plesiochronous construction circuit for decreasing the delay time of network intervals in the time of reframing the frame signal has a memory region for recording the received data RD by inputting the receiving clock RCK. The clock difference in the intervals of system is compensated by outputting the data recorded at memory region. The elastic buffer (10) outputs the state alarm signal of the memory region. The half-full counter (20) generates the gate control signal. The gate (30) provides the system clock SCK of system clock line (11) to the lead clock terminal. The frame alignment signal detector (40) generates the synchronous break signal or the synchronization signal.

Description

Independent Synchronization Circuit Eliminates Delay of Buffer During Reframe

1 is a circuit diagram according to the present invention.

2 is an operational waveform diagram of a portion of FIG.

* Explanation of symbols for main parts of the drawings

10: Elastic buffer 20: Half-full counter

30: 3-state buffer 40: frame array signal detection unit

50: NAND gate 60: flip-flop

70, 80: Andgate

The present invention relates to an independent synchronization scheme for reducing delay time between networks when a frame signal is reframed due to an error in a intensive communication network.

In general, in order to transmit and receive information between exchange systems that process voice and data, synchronization between a transmission system for transmitting data information and a means system for receiving the data is required. Because the exchange system that transmits / receives digital information transmits the data or voice data of many subscribers through the multiplexing device, a problem occurs that the receiving system does not know the start of data unless synchronization between the transmitting and receiving systems is achieved. As a result, data cannot be exchanged with each other. Therefore, the network system must be synchronized with each other so that smooth communication can be executed. Ideally, a network synchronizer means that all transmission and switching systems in a network move (move) at the same clock, but in practice, it is very difficult to operate the same clock when configuring a switching network with multiple switching systems. Currently, there are two types of synchronization methods that synchronize the exchange system with the slave system: slave synchronization and lesiochronous.

Subordinate synchronizations such as the former provide a clock source of one switching system as a main clock source in a network composed of a plurality of switching systems, and provide the operation of all switching systems according to the main clock source. This is how it works. The biggest disadvantage of the slave synchronization is that if the output of the main clock source fails in the transmission signal, the lower switching system operated according to the clock source does not operate.

The latter independent synchronization method buffers the clock stability difference between systems by maintaining synchronization with clock sources independent of each other in each exchange system constituting a network in digital communication network. To compensate for this by using memory (Buffer memory).

In the conventional synchronous circuit, the independent synchronization circuit detects the frame array signal from the data received from the counterpart system first and then uses both systems (Elastic Store: Buffer memory). Since the clock stability of the transmission and reception system) has been taken, there have been the following problems. When an error occurs in a frame due to a intensive error, an out of sync signal is generated by a frame alignment signal detector that detects the frame arrangement, thereby resetting the elastic buffer. After the data is received without error, when the frame array signal detection unit finds synchronization in the received signal and outputs an in-sync signal, the elastic buffer is operated to store the received signal. At this time, since the elastic buffer writes the input data to half of the total storage area and transmits the data, the delay is inevitable by half the size of the elastic buffer. Accordingly, an object of the present invention is to provide an independent synchronous method that can eliminate the delay time between communication networks by a memory buffer when the system reconfigures a received signal in a communication network with multiple networks and frequent burst errors. In providing a circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 is a circuit diagram according to the present invention, which has a storage area of a predetermined size, stores received data RD in the storage area by a reception clock RCK input, and stores data in the storage area by a read clock input. Compensating the clock difference between the system by outputting the signal, and counting up to 1/2 of the storage size of the elastic buffer 10 and the receiving buffer RCK to output the status notification signal of the storage area; A half full counter 20 which generates a gate control signal is connected between a system clock line 11 and a lead clock terminal of the elastic buffer 10 and is input by the gate control signal. A gate 30 which is enabled to provide a system clock SCK of the system clock line 11 to the lead clock terminal, an output terminal of the elastic buffer 10 and the system clock line 11; The system clock SCK of the system clock line 11 is divided to output a frame clock, and the frame array is detected by the frame clock to generate an out of sync or in-sync signal. Data arranged between a frame array signal detector 40, an output terminal of the elastic buffer 10, and a system receiving end, and transmitting the output of the elastic buffer 10 to the system by a system synchronization enable signal. It is connected to a transmission gate 90 and an output terminal of the frame array signal detector 40, and is enabled by the in-sync signal and latches a system frame synchronization signal by a frame clock to transmit the signal. The elastic buffer 1 is inputted by the data transfer controller 60 outputting the enable signal of the gate 90 and the state alarm signal of the elastic buffer 10. 0) and the AND gates 70 and 80 for resetting the half pull counter 20.

In the configuration of FIG. 1, the reference numeral RD denotes received data transmitted from the counterpart switching system, and RCK denotes a signal extracted from the received data as a received clock. SCK is a system clock of a system that processes the received data, and Fsync is a frame synchronization signal of the system. At this time, the system clock SCK of the received clock RCE is 1.024MEZ, and the frame has a period of 32 ms. 2 is an operation waveform diagram of a part of FIG. 1, (a) is a frame synchronization signal FSYNC of the system, (b) is a 32 kHz frame clock divided by 1.024 MEZ, and (c) is (D) is data output from the elastic buffer 10, (e) is a signal obtained by inverting the frame clock 32 s output delayed by 488 nSec from the frame array signal detector 40, (f) is an in-sync signal outputted when the frame array signal detector 40 continuously detects 128 frames of the frame array signal, and (g) is a data transfer controller composed of D-flip flops. 60 is the synchronization enable control signal, and (h) is the output of the transmission gate 90.

Hereinafter, an operation example of FIG. 1 according to the present invention will be described in detail with reference to FIG. 2. The data transmitted from the other party's switching system is now received, and the received data RD is input to the line 3. At this time, the reception clock RCK extracted from the data is input to the line 5, and the reception clock RCK is a transmission clock of a speed transmitted from the counterpart switching system. At this time, the elastic buffer 10 stores the received data RD input to the line 3 in the internal temporary storage area by the receive clock input to the line 5. Such an elastic buffer 10 may be configured as a first-in first-out (FIFO). On the other hand, the half-full counter 20 counts the received clock RCK input to the line 5, and when the clock corresponding to 1/2 of the storage area of the elastic buffer 10 is counted, the gate control " low, high Is output to the line 7.

The three-state buffer 30 for inputting the gate control signal " low " of the half-pull counter 20 is enabled, and the system clock SCK input to the system clock line 11 is inputted to the elastic buffer. Input the lead terminal (RD) of 10). Accordingly, the received data written to the elastic buffer 10 is read as shown in FIG. 2D by the system clock SCK input to the lead terminal RD, so that the frame array signal detection unit 40 and the transmission gate 90 can be read. Will be displayed. Therefore, the system reads data regardless of the clock of the counterpart exchange.

프레임 클럭으로 수신 데이타를 클럭킹하여 연속적으로 128프레임의 채널ø(channel ø)가 검출되면 동기잡힘(In-sync)의 논리 "하이"을 제2f도와 같이 출력한다. 만약 초기상태에서 연속 8개의 프레임이 에러이거나 동기잡힘상태에서 연속 16프레임이 에러일때에는 동기이탈(out-of-sync)을 상기 프레임 배열신호검출기(40)로 부터 출력된다. 한편 프레임 배열신호 검출기(40)로 부터 출력되는 제2c도와 같은 반전신호(프레임 클럭 32KHZ)과 제2f도와 같은 동기잡힘신호(In-sync)를 입력하는 낸드게이트(50)의 상기 프레임 클럭 32KHZ을

로 반전하여 상기 동기잡힘신호(In-sync)에 의해 클리어가 해제되는 데이타 전송제어기(60)의 클럭단자로 출력된다. 이때 상기 데이타 전송제어기(60)는 입력단자(D)로 입력되는 제2a도와 같은 시스템의 프레임 동기(FSYNC)를 클럭킹하여 프레임 배열신호 검출기(40)에서 동기잡힘 신호를 출력하기전까지 논리 "하이"로 출력하였던 시스템 동기 인에이블 신호를 제2g도와 같이 "로우"로 천이시키어 시스템 동기신호(FSYNC)에 동기된 신호를 전송게이트(90)로 입력시킨다.On the other hand, the frame array signal detector 40 detects the frame array signal inserted into the received signal at regular intervals and according to the detection state of the logic array high in-sync or out of the logic low out-of-sync A signal is output to the line 15, and the system clock SCK is divided to output a frame clock as shown in FIG. At this time, the frame array signal detector 40 is composed of a shift register and an up / down counter.

When the received data is clocked by the frame clock and the channel? Of 128 frames is continuously detected, the logic " high " of in-sync is output as shown in FIG. 2f. If eight consecutive frames are in an initial state or 16 consecutive frames are in an error state, an out-of-sync is output from the frame array signal detector 40. Meanwhile, the frame clock 32KHZ of the NAND gate 50 for inputting an inverted signal (frame clock 32KHZ) as shown in FIG. 2C and a synchronization signal (In-sync) as shown in FIG. 2F as output from the frame array signal detector 40 is used.

Inverted to and outputted to the clock terminal of the data transfer controller 60 is cleared by the synchronization signal (In-sync). At this time, the data transmission controller 60 clocks the frame synchronization (FSYNC) of the system as shown in FIG. 2A input to the input terminal D, and the logic "high" until the frame array signal detector 40 outputs the synchronization signal. The system synchronous enable signal, which has been outputted by the signal, is shifted to " low " as shown in FIG. 2g, and a signal synchronized with the system synchronous signal FSYNC is input to the transmission gate 90.

At this time, the transmission gate 90 transmits the channel? Signal of the frame signal synchronized with the system synchronization signal among the output signals output from the elastic buffer 10 to the receiving end of the system. Therefore, the present invention compensates for the clock stability difference between the two systems using the elastic buffer 10, and outputs the output in synchronization with the synchronization signal of the system, the elastic buffer 10, regardless of the frame lost due to burst errors By operating the elastic buffer 10, independent synchronization is realized by eliminating the delay difference caused by the buffer at the time of reframe.

As described above, the present invention compensates the difference in clock stability between systems by using a memory buffer and preferentially compensates for received data that is bit-synchronized when an error is reframed by an error in a intensively error-prone communication network, and improves frame synchronization in a frame array signal detector. Independent synchronization can be realized by eliminating the delay caused by the memory buffer by searching and synchronizing the system.

Claims (1)

An independent synchronous circuit that eliminates delays in buffers when reframed, has a storage area of a predetermined size, receives data RD in the storage area by a receive clock RCK input, and stores in the storage area by a read clock input. Compensates the clock difference between systems by outputting data, and counts up to 1/2 of the storage size of the elastic buffer 10 and the receiving buffer RCK for outputting a state alarm signal of the storage area. And a half-full counter 20 for generating a gate control signal, a system clock line 11 and a lead clock terminal of the elastic buffer 10, and are enabled by the gate control signal input. A gate 30 providing the system clock SCK of the clock line 11 to the lead clock terminal, an output terminal of the elastic buffer 10 and the system clock line; A frame array signal detector connected to (11), which divides the system clock SCK of the system clock line 11 to output a frame clock, detects the frame arrangement with the frame clock, and generates a synchronous deviation or a catch signal; A data transfer gate 90 connected between the system receiving terminal of the output terminal of the elastic buffer 10 and transmitting the output of the elastic buffer 10 to the system by a system synchronization enable signal; And an output terminal of the frame array signal detector 40, which is enabled by the synchronization signal and latches a system frame synchronization signal by a frame clock to output the enable signal of the transmission gate 90. The elastic buffer 10 and the half full count are input by the data transfer controller 60 and the state alarm signal of the elastic buffer 10 described above. And an AND gate (70, 80) for resetting the rotor (20).

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