KR920006251B1 - Level shift circuit - Google Patents

Level shift circuit Download PDF

Info

Publication number
KR920006251B1
KR920006251B1 KR1019890015443A KR890015443A KR920006251B1 KR 920006251 B1 KR920006251 B1 KR 920006251B1 KR 1019890015443 A KR1019890015443 A KR 1019890015443A KR 890015443 A KR890015443 A KR 890015443A KR 920006251 B1 KR920006251 B1 KR 920006251B1
Authority
KR
South Korea
Prior art keywords
signal
pmos transistor
constant voltage
level
charge
Prior art date
Application number
KR1019890015443A
Other languages
Korean (ko)
Other versions
KR910008842A (en
Inventor
박용보
Original Assignee
삼성전자 주식회사
김광호
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 김광호 filed Critical 삼성전자 주식회사
Priority to KR1019890015443A priority Critical patent/KR920006251B1/en
Priority to JP2047084A priority patent/JPH03147419A/en
Priority to GB9004352A priority patent/GB2238681B/en
Priority to FR909002441A priority patent/FR2653951B1/en
Priority to DE4006144A priority patent/DE4006144A1/en
Publication of KR910008842A publication Critical patent/KR910008842A/en
Application granted granted Critical
Publication of KR920006251B1 publication Critical patent/KR920006251B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)

Abstract

The level converter for converting a TTL level of input signal to a CMOS level comprises a NOR gate circuit (1), including a first voltage pull-up PMOS transistor (PI2), to which the TTL signal is inputted, an inverter (INV) connected to the NOR gate circuit, and a speed control circuit (2). The NOR gate circuit has a PMOS (PI1) and an NMOS (NI1) controlled by a control signal (CS), as well as a CMOS transistor (PI2, NI2) fed by the TTL signal. The speed control circuit includes a second voltage pull-up PMOS transistor (PI4). The two transistors (PI2,PI4) are connected in parallel between VCC and the input to the inverter. A fast conversion speed is obtained by turning on both PMOS (PI2,PI4) when the TTL signal goes from the high level to the low level.

Description

레벨변환기Level converter

제1도는 종래의 레벨변환기를 나타낸 상세회로도.1 is a detailed circuit diagram showing a conventional level converter.

제2도는 본 발명의 레벨변환기를 나타낸 상세회로도.2 is a detailed circuit diagram showing a level converter of the present invention.

제3도는 종래의 레벨변환기를 동작과 본 발명의 레벨변환기의 동작을 비교하여 설명하기 위한 타이밍도이다.3 is a timing diagram for explaining and comparing the operation of the conventional level converter with the operation of the level converter of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 노아게이트회로 2 : 속도제어회로1: Noah gate circuit 2: Speed control circuit

3 : 충방전부 4 : 정전압부3: charge and discharge unit 4: constant voltage unit

5 : 속도제어부 C : CMOS 트랜지스터5: speed control part C: CMOS transistor

CS : 제어신호 A : 본 발명의 출력파형곡선CS: control signal A: output waveform curve of the present invention

B : 종래의 출력파형곡선 IN : 입력단자B: Conventional output waveform curve IN: Input terminal

lNV : 인버터 OUT : 출력단자lNV: Inverter OUT: Output terminal

R : 저항 VR : 정전압R: resistance VR: constant voltage

VNOR : 노아게이트 출력단자 NI1∼NI3 : NMOS트랜지스터VNOR: NOR gate output terminals NI1 to NI3: NMOS transistor

PI1∼PI4 : PMOS트랜지스터PI1 to PI4: PMOS transistor

본 발명은 반도체 칩에 관한 것으로, 특히 입력되는 TTL신호레벨을 CMOS신호레벨을 변환시키는데 변환속도를 빠르게 하기위한 레벨변환기에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly, to a level converter for converting an input TTL signal level into a CMOS signal level to speed up a conversion speed.

일반적으로 CMOS 반도체칩에서는 입력되는 TTL신호의 레벨이 0.8V이하이면 로직저레벨로, 2.2V이상이면 로직하이레벨로서 정의되고 CMOS신호레벨은 OV이하이면 로직저레벨로 5V이상이면 로직하이레벨로서 정의되므로 TTL신호레벨이 입력될때 입력된 TTL신호를 CMOS신호레벨로 변환시키는 레벨변환기가 필요하다.In general, in the case of CMOS semiconductor chip, the input TTL signal is defined as logic low level when 0.8V or less, and logic high level when 2.2V or more, and CMOS signal level is defined as logic high level when 5V or more. When the TTL signal level is input, a level converter is required to convert the input TTL signal into a CMOS signal level.

종래의 레벨변환기는 제l도에 나타낸 바와 같이 노아게이트회로(1)로 구성하여 입력된 TTL신호레벨을 풀업(pull-up) 및 풀다운(pull-down)시켜 CMOS신호레벨로 변환시킨다. 그러나, 입력된 TTL신호레벨이 고신호레벨인 2.2V이면 풀업시키는 PMOS트랜지스터(PI2)와 풀다운시키는 NMOS트랜지스터(NI2)가 동시에 턴온되므로 출력인 로직을 저레벨로 유지하기 위하여는 PMOS트랜지스터(PI2)가 NMOS트랜지스터(NI2)에 비해 크기가 작아야 한다. 따라서, NMOS트랜지스터(NI2)에 비해 상대적으로 작은 PMOS트랜지스터(PI2)의 크기는 입력된 TTL신호가 고레벨(high)에서 저레벨(Low)로 전환될때 노아게이트회로(1)의 출력이 저레벨에서 고레벨로 변환되는 속도가 늦어진다. 따라서 반도체칩의 고속화하려는 추세에 역행하는 문제점이 발생하였다.The conventional level converter is configured by the no-gate circuit 1 as shown in FIG. 1 to pull up and pull down the input TTL signal level to convert it into a CMOS signal level. However, if the input TTL signal level is 2.2V, which is a high signal level, the PMOS transistor PI2 for pulling up and the NMOS transistor NI2 for pulling down are turned on at the same time, so that the PMOS transistor PI2 is maintained to maintain the output logic at a low level. It should be smaller than the NMOS transistor (NI2). Therefore, the size of the PMOS transistor PI2, which is relatively small compared to the NMOS transistor NI2, is that when the input TTL signal is switched from high level to low level, the output of the NOA gate circuit 1 goes from low level to high level. The speed of conversion slows down. Therefore, a problem has arisen in opposition to the trend of increasing the speed of semiconductor chips.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 입력되는 TTL신호레벨을 CMOS신호레벨로 변환시키는데 변환되는 속도가 빠르도록한 레벨변환기를 제공하고자 함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a level converter which converts an input TTL signal level into a CMOS signal level so that the conversion speed is high.

본 발명의 또 다른 목적은 레벨변환기의 속도를 제어하는 속도제어회로를 간단하게 설계하여 기존의 반도체칩의 레벨변환기에 널리 용이하게 사용할 수 있는 레벨변환기를 제공하고자 함에 있다. 이러한 본 발명의 목적은 TTL신호입력단자와 출력단자에 연결된 인버터와 TTL신호 입력단자 사이에 속도제어 회로를 연결함으로서 달성될 수 있다.It is still another object of the present invention to provide a level converter that can be easily used in a level converter of a conventional semiconductor chip by simply designing a speed control circuit for controlling the speed of the level converter. This object of the present invention can be achieved by connecting the speed control circuit between the TTL signal input terminal and the inverter connected to the output terminal and the TTL signal input terminal.

본 발명의 특징은 제어신호에 의하여 제어되는 PMOS트랜지스터와, NMOS트랜지스터, TTL신호를 입력으로 하는 PMOS트랜지스터와 NMOS트랜지스터로 구성된 노아게이트회로와 상기 노아게이트회로의 출력단자에 연결된 인버터와 연결 구성된 레벨변환기에 있어서, 입력된 TTL신호에 의하여 충방전되는 충방전부와, 상기 충방전부의 출력단자에 정전압을 설정하기 위한 정전압부와, 상기 충방전부의 출력단자에 정전압을 설정하기 위한 정전압부와 상기 충방전부의 충방전전압과 정전압부의 정전압에 의하여 레벨변화기의 변환속도가 제어되는 속도제어와 연결구성된 레벨변환기에 있다.The present invention is characterized in that a PMOS transistor controlled by a control signal, a NMOS transistor, a NOR transistor comprising a PMOS transistor and an NMOS transistor as inputs, and an inverter connected to an output terminal of the NOR gate circuit are configured as a level converter. The charge / discharge unit charged and discharged by the input TTL signal, a constant voltage unit for setting a constant voltage at the output terminal of the charge and discharge unit, a constant voltage unit for setting a constant voltage at the output terminal of the charge and discharge unit and the charge and discharge unit The level converter is connected to the speed control in which the conversion speed of the level changer is controlled by the charge / discharge voltage of the constant voltage part and the constant voltage of the constant voltage part.

이하 본 발명의 실시예를 첨부된 도면에 의하여 상세하게 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제1도는 종래의 레벨변환기를 나타낸 상세회로도로서, 레벨변환기를 구동시키기 위한 제어신호(CS)가 PMOS트랜지스터(PI1)와 NMOS트랜지스터(NI1)의 각 게이트측에 인가되도록 연결되어 있다. 그리고 상기 PMOS트랜지스터(PI1)의 드레인측과 상대 접지전압(VSS)사이에 0.8V2.2V 사이에서 동작되는 TTL신호를 풀입 및 풀다운시키는 풀업용 PMOS트랜지스터(Pl2)와 풀다운용 NMOS트랜지스터(Nl2)로 구성된CMOS트랜지스터(C)가 연결되어 있다.FIG. 1 is a detailed circuit diagram showing a conventional level converter. The control signal CS for driving the level converter is connected to each gate side of the PMOS transistor PI1 and the NMOS transistor NI1. And a pull-up PMOS transistor (Pl2) and a pull-down NMOS transistor (Nl2) for pulling in and pulling down a TTL signal operating between 0.8V2.2V between the drain side of the PMOS transistor PI1 and the relative ground voltage VSS. The configured CMOS transistor C is connected.

상기 CMOS트랜지스터(C)의 출력에 풀업 또는 풀다운된 출력신호를 반전하는 인버터(INV)가 연결되어 있다. 이때 PMOS트랜지스터(PI1, PI2) 및 NMOS트랜지스터(NI1, NI2)는 노아게이트회로(1)로 구성된다.An inverter INV for inverting a pulled up or pulled down output signal is connected to the output of the CMOS transistor C. At this time, the PMOS transistors PI1 and PI2 and the NMOS transistors NI1 and NI2 are constituted by the NOR gate circuit 1.

이상에서와 같이 구성된 레벨변환기는 레벨변환기를 제어하는 제어신호(CS)가 고레벨신호로 PMOS트랜지스터(PI1)와 NMOS트랜지스터(Nl1)의 게이트측에 인가되면 레벨변환기를 구동되지 않는다. 그러나 레벨변환기의 제어신호(CS)가 저레벨신호이면 레벨변환기는 인에이블(enaIbe)되고 따라서, 레벨변환기가 구동되어 입력된 TTL신호레벨을 CMOS신호 레벨로 변환된다. 즉, 입력된 TTL신호가 저레벨신호이면 CMOS트랜지스터(C)의 PMOS트랜지스터(PI2)가 턴온되어 노아게이트회로(1)의 출력전압은 풀업되고 따라서 CMOS신호레벨은 5V의 고레벨전위로 출력된다. 그리고, 노아게이트회로(1)의 출력된 고레벨 전위는 인버터(INV)에 의하여 반전된다. 그러나 입력된 TTL신호가 고레벨신호인 2.2V이면 PMOS트랜지스터(PI2)와 NMOS트랜지스터(NI2)가 동시에 턴온되므로 출력인 로직을 저레벨로 유지시키기 위하여는 PMOS트랜지스터(PI2)의 크기가 NMOS트랜지스터(NI2)보다 작게 설계하여야 한다.The level converter configured as described above does not drive the level converter when the control signal CS for controlling the level converter is applied to the gate side of the PMOS transistor PI1 and the NMOS transistor N11 as a high level signal. However, if the control signal CS of the level converter is a low level signal, the level converter is enabled and thus the level converter is driven to convert the input TTL signal level into a CMOS signal level. That is, if the input TTL signal is a low level signal, the PMOS transistor PI2 of the CMOS transistor C is turned on, and the output voltage of the NOA gate circuit 1 is pulled up, and thus the CMOS signal level is output at a high level potential of 5V. Then, the high level potential output of the NOA gate circuit 1 is inverted by the inverter INV. However, if the input TTL signal is 2.2V, which is a high level signal, the PMOS transistor PI2 and the NMOS transistor NI2 are turned on at the same time, so that the size of the PMOS transistor PI2 is NMOS transistor NI2 to maintain the output logic at a low level. It should be designed smaller.

즉, PMOS트랜지스터(PI2) 크기가 NMOS트랜지스터(NI2)보다 작으므로 입력된 고레벨의 TTL신호는 NMOS트랜지스터(NI2)를 PMOS트랜지스터(PI2)보다 강하게 턴온시켜 노아게이트회로(1)의 출력전압(VNOR)이 풀다운된다. 따라서, 노아게이트회로(1)의 출력신호는 저레벨로 출력되고 출력된 저레벨신호는 인버터(INV)에 의하여 반전, CMOS신호레벨은 고레벨신호로 출력된다. 그러나, NMOS트랜지스터(NI2)의 크기에 비해 작은 PMOS트랜지스터(PI2)는 입력신호(IN)가 저레벨신호에서 고레벨신호로 변환될때의 출력속도는 빠르나 입력신호(IN)가 고레벨신호에서 저레벨신호로 전환될때의 출력속도는 느리게 되는 원인이 된다.That is, since the size of the PMOS transistor PI2 is smaller than that of the NMOS transistor NI2, the input high-level TTL signal turns on the NMOS transistor NI2 more strongly than the PMOS transistor PI2, thereby outputting the output voltage VNOR of the no-gate circuit 1. ) Is pulled down. Therefore, the output signal of the NOA gate circuit 1 is output at a low level, the output low level signal is inverted by the inverter INV, and the CMOS signal level is output as a high level signal. However, the PMOS transistor PI2 which is smaller than the size of the NMOS transistor NI2 has a high output speed when the input signal IN is converted from a low level signal to a high level signal, but the input signal IN is converted from a high level signal to a low level signal. Output speed is slow.

제2도는 본 발명의 레벨변환기를 나타낸 상세회로도로서, 레벨변환기를 구동시키기 위한 제어신호(CS)가 PMOS트랜지스터(PI1)와 NMOS트랜지스터(NI1)의 각 게이트단자에 인가되도록 연결시킨다. 그리고, 상기 PMOS트랜지스터(PI1)의 드레인측과 상대 접지전압(VSS) 사이에 0.8V∼2.2V 사이에서 동작되는 TTL신호를 풀업 및 풀다운시키기 위한 풀업용 PMOS트랜지스터(PI2)와 풀다운용 NMOS트랜지스터(NI2)로 구성된 CMOS트랜지스터(C)를 연결시킨다. 이때, 상기 PMOS트랜지스터(PI1, PI2) 및 NMOS트랜지스터(NI1,NI2)는 노아게이트(1)로 구성된다. 그리고, 상기 노아게이트회로(1)의 출력신호를 반전시키는 인버터(INV)로 구성된 레벨변환기의 입력된 TTL신호에 의하여 충방전되는 충방전부(3)의 충방전용 PMOS트랜지스터(PI3)를 연결시킨다. 상기 충방전부(3)의 충방전용 PMOS트랜지스터(PI3)의 드레인과 소오스측을 연결시킨다. 그리고 상기 충방전부(3)의 출력단자에 항상 일정한 전압을 만드는 정전압부(4)를 연결시킨다.2 is a detailed circuit diagram illustrating a level converter of the present invention, in which a control signal CS for driving the level converter is connected to each gate terminal of the PMOS transistor PI1 and the NMOS transistor NI1. A pull-up PMOS transistor PI2 and a pull-down NMOS transistor for pulling up and pulling down a TTL signal operating between 0.8V and 2.2V between the drain side of the PMOS transistor PI1 and the relative ground voltage VSS. Connect a CMOS transistor (C) consisting of NI2). In this case, the PMOS transistors PI1 and PI2 and the NMOS transistors NI1 and NI2 are constituted by a noah gate 1. Then, the charge / discharge PMOS transistor PI3 of the charge / discharge unit 3 charged / discharged by the input TTL signal of the level converter composed of the inverter INV for inverting the output signal of the NOA gate circuit 1 is connected. The drain and the source side of the charge / discharge PMOS transistor PI3 of the charge / discharge unit 3 are connected. Then, the constant voltage unit 4 which always makes a constant voltage is connected to the output terminal of the charge / discharge unit 3.

상기 정전압부(4)는 정전원(VCC)이 드레인과 게이트측에 각각 인가되어 항상 턴온되는 스위칭용 NMOS트랜지스터(NI3)를 연결시키고, 상기 스위칭용 NMOS트랜지스터(NI3)의 소오스측에는 바이어스용 고저항(R)을 연결시켜 정전압부(4)의 출력전압인 정전압(VR)이 항상 일정하게 출력되도록 구성시킨다. 이때, 충방전부(3)의 PMOS트랜지스터(PI3)의 연결된 드레인과 소오스측은 정전압부(4)의 저항(R)의 출력단자와 연결시킨다. 그리고 상기 충방전부(3)의 PMOS트랜지스터(PI3)의 입력신호에 대한 커플링(coupling)에 따라 턴온 또는 턴오프되는 PMOS트랜지스터(PI4)로 구성된 속도 제어부(5)을 연결시킨다. 상기 속도제어부(5)은 상기 정전압 부(4)의 출력전압을 PMOS트랜지스터(PI4)의 게이트측에 인가되도록 연결시키고 PMOS트랜지스터(PI4)의 드레인측은 CMOS트랜지스터(C)의 출력단자와 연결시킨다. 이때, 충방전부(3),정전압부(4) 및 속도제어부(5)는 속도제어회로(2)로 구성시킨다.The constant voltage unit 4 connects the switching NMOS transistor NI3 that is always turned on by applying the electrostatic source VCC to the drain and gate sides, and has a high resistance for bias on the source side of the switching NMOS transistor NI3. (R) is connected so that the constant voltage VR, which is the output voltage of the constant voltage unit 4, is always output constantly. At this time, the connected drain and the source side of the PMOS transistor PI3 of the charge / discharge unit 3 are connected to the output terminal of the resistor R of the constant voltage unit 4. In addition, the speed controller 5, which is configured to be turned on or off according to the coupling of the input signal of the PMOS transistor PI3 of the charge / discharge unit 3, is connected to the speed controller 5. The speed controller 5 connects the output voltage of the constant voltage unit 4 to be applied to the gate side of the PMOS transistor PI4 and the drain side of the PMOS transistor PI4 to the output terminal of the CMOS transistor C. At this time, the charge / discharge unit 3, the constant voltage unit 4 and the speed control unit 5 is composed of a speed control circuit (2).

이상에서와 같이 구성된 본 발명의 작용효과를 상세하게 설명하면 다음과 같다. 레벨변환기를 인에이블시키는 제어신호(CS)가 고레벨신호가 되면 노아게이트회로(1)의 PMOS트랜지스터(PI1)와 NMOS트랜지스터(Nl1)가 동시에 턴오프되어 레벨변환기를 디스에이블된다. 그러나 제어신호(CS)가 저레벨신호이면 레벨변환기는 인에이블된다. 이와 같이 레벨 환기가 인에이블되고 입력된 TTL신호가 저신호이면 노아게이트회로(1)의 출력신호는 풀업된 고레벨신호가 출력되며 노아게이트회로(1)에서 출력된 풀업 고레벨신호는 인버터(INV)에 의하여 저레벨신호로 반전된다. 그러나 입력된 TTL신호가 고레벨이면 CMOS트랜지스터(C)의 PMOS트랜지스터(PI2)와 NMOS트랜지스터 (NI2)가 동시에 턴온되나 PMOS트랜지스터(PI2)가 NMOS트랜지스터(NI2)보다 크기가 작아 NMOS트랜지스터(NI2)가 PMOS트랜지스터(PI2)보다 강하게 턴온된다. 따라서, 입력된 TTL고레벨신호는 노아게이트회로(1)의 NMOS트랜지스터(NI2)에 의하여 풀다운되어 저레벨신호로 출력된다. 그리고, 노아게이트회로(1)의 출력된 신호는 인버터(INV)에 의하여 반전된다.Referring to the effect of the present invention configured as described above in detail as follows. When the control signal CS for enabling the level converter becomes a high level signal, the PMOS transistor PI1 and the NMOS transistor Nl1 of the NOA gate circuit 1 are simultaneously turned off to disable the level converter. However, if the control signal CS is a low level signal, the level converter is enabled. When the level ventilation is enabled and the input TTL signal is a low signal, the pull-up high level signal output from the no-gate circuit 1 is output as the output signal of the no-gate circuit 1 and the inverter INV Is inverted to a low level signal. However, if the input TTL signal is at a high level, the PMOS transistor (PI2) and the NMOS transistor (NI2) of the CMOS transistor (C) are turned on at the same time, but the PMOS transistor (PI2) is smaller than the NMOS transistor (NI2), so the NMOS transistor (NI2) becomes smaller. It is turned on more strongly than the PMOS transistor PI2. Therefore, the input TTL high level signal is pulled down by the NMOS transistor NI2 of the no-gate circuit 1 and output as a low level signal. The output signal of the NOA gate circuit 1 is inverted by the inverter INV.

이때 입력된 TTL신호가 저레벨신호가 고레벨신호로 전환되면 CMOS트랜지스터(C)의 PMOS트랜지스터(PI2)와 NMOS트랜지스터(NI2)는 모두 턴온되나 NMOS트랜지스터(NI2)의 크기에 의하여 노아게이트회로(1)의 출력신호(VNOR)는 로직 저레벨이 된다. 그리고 입력된 TTL신호는 충방전부(3)의 충방전용 PMOS트랜지스터(PI3)의 게이트측에 인가된다.At this time, when the input TTL signal is converted into a high level signal, both the PMOS transistor PI2 and the NMOS transistor NI2 of the CMOS transistor C are turned on, but the noar gate circuit 1 is turned on by the size of the NMOS transistor NI2. The output signal of VNOR becomes the logic low level. The input TTL signal is applied to the gate side of the charge / discharge PMOS transistor PI3 of the charge / discharge unit 3.

이때, 상기 정전압부(4)의 출력전압(VR)은 NMOS트랜지스터(NI3)의 임계전압(VIN)과 NMOS트랜지스터(NI3)의 드레인과 게이트측에 연결된 정전압(VCC)와 백바이어스 전압(VBB)의 차로서 항상 유지된다. 즉, VR=Vcc-Vin-VBB이다. 따라서, 충방전부(3)의 충방전 전압과 정전압부(4)의 정전압(VR)에 의하여 후단에 연결된 속도제어부(5)의 인가전압은 정전압부(4)의 정전압(VR)이상이 되고, 이 정전압(VR)은 속도제어부(5)의 PMOS트랜지스터(PI4)의 게이트에 인가되므로 속도제어부(5)의 PMOS트랜지스터(PI4)는 오프된다.In this case, the output voltage VR of the constant voltage unit 4 includes the threshold voltage VIN of the NMOS transistor NI3 and the constant voltage VCC and the back bias voltage VBB connected to the drain and gate side of the NMOS transistor NI3. Is always kept as a difference. That is, VR = Vcc-Vin-V BB . Therefore, the voltage applied to the speed controller 5 connected to the rear end by the charge / discharge voltage of the charge / discharge unit 3 and the constant voltage VR of the constant voltage unit 4 is equal to or greater than the constant voltage VR of the constant voltage unit 4, The constant voltage VR is applied to the gate of the PMOS transistor PI4 of the speed controller 5, so that the PMOS transistor PI4 of the speed controller 5 is turned off.

그러나 입력된 고레벨신호에서 저레벨신호로 변환되면 노아게이트회로(1)의 CMOS트랜지스터(C)의 NMOS트랜지스터(NI2)는 오프되고 PMOS트랜지스터(PI2)는 온되어 노아게이트회로(1)의 출력신호(VNOR)은 고레벨이 되나 PMOS트랜지스터(PI2)의 크기에 의하여 속도가 느리다.However, when the input high level signal is converted into a low level signal, the NMOS transistor NI2 of the CMOS transistor C of the NOR gate circuit 1 is turned off, and the PMOS transistor PI2 is turned on to output the output signal of the NOG gate circuit 1. VNOR) is high level but is slow due to the size of the PMOS transistor (PI2).

이때, 충방전부(3)의 충방전용 PMOS트랜지스터(PI3)는 입력신호 따라 커플링(coupling)되고 따라서 정전압부(4)에 의하여 출력되는 정전압(VR)은 입력전압의 파형과 같이되어 속도제어부(5)의 PMOS트랜지스터(PI4)를 턴온시킬만큼 낮아져 속도제어부(5)의 PMOS트랜지스터(PI4)는 턴온된다. 즉, 속도제어부(5)의 PMOS트랜지스터(PI4)의 게이트측에 인가되는 전압은 정전압부(4)의 출력전압(VR)보다 낮아져 속도제어부(5)의 PMOS트랜지스터(PI4)는 턴온된다.At this time, the charge / discharge PMOS transistor PI3 of the charge / discharge unit 3 is coupled according to the input signal, and thus the constant voltage VR output by the constant voltage unit 4 becomes a waveform of the input voltage and thus the speed control unit ( The PMOS transistor PI4 of 5) is turned low so as to turn on, so that the PMOS transistor PI4 of the speed controller 5 is turned on. That is, the voltage applied to the gate side of the PMOS transistor PI4 of the speed controller 5 is lower than the output voltage VR of the constant voltage unit 4, so that the PMOS transistor PI4 of the speed controller 5 is turned on.

따라서, 입력된 TTL신호가 고레벨에서 저레벨신호로 떨어질때 노아게이트회로(1)의 CMOS트랜지스터(C)의 PMOS트랜지스터(PI2)와 속도제어회로(2)의 속도제어부(5)의 PMOS트랜지스터(PI4)가 동시에 턴온되어 풀다운된 저레벨신호를 출력시키는 속도가 매우 빠르다.Therefore, when the input TTL signal falls from the high level to the low level signal, the PMOS transistor PI2 of the CMOS transistor C of the NOA gate circuit 1 and the PMOS transistor PI4 of the speed control part 5 of the speed control circuit 2 are generated. Are simultaneously turned on to output a pulled-down low level signal.

또한 일정시간이 지난후에 정전압수단(2)의 출력전압(VR)이 회복되어 속도제어부(5)의 트랜지스터(PI4)가 턴오프되나 이미 노아게이트회로(1)의 CMOS트랜지스터(C)의 출력은 충분히 고레벨이 된다.In addition, after a predetermined time, the output voltage VR of the constant voltage means 2 recovers and the transistor PI4 of the speed controller 5 is turned off, but the output of the CMOS transistor C of the noah gate circuit 1 is already It is high enough level.

이상에서와 같이 입력된 TTL신호레벨을 CMOS의 신호레벨로 변환하는데 있어서 입력된 TTL신호가 고레벨신호일때 풀다운된 저레벨신호를 노아게이트회로(1)에서 출력시키기 위하여 NMOS트랜지스터 보다 PMOS트랜지스터 크기가 작게 설계되어 입력된 TTL신호가 고레벨신호에서 저레벨신호로 전환될때의 출력의 상승시간(rising time)이 늦어져 전체의 변환 속도가 늦어지던 것을 본 발명은 입력된 TTL신호가 고레벨신호에서 저레벨신호로 전환될때 턴온되는 노아게이트회로의 CMOS트랜지스터와 동시에 속도 제어회로의 속도제어부의 PMOS트랜지스터를 턴온시켜 상승시간을 빠르게 하여 레벨을 변환시키는 전체의 속도를 빠르게 할 수 있다. 그리고 충방전용 PMOS트랜지스터와 정전압부 및 속도제어부로 구성된 속도제어회로가 간단하게 구성되어 있어 기존의 레벨변환기에 용이하게 사용할 수 있는 효과가 있다.As described above, in converting the input TTL signal level to the signal level of CMOS, the PMOS transistor size is smaller than that of the NMOS transistor to output the pulled low level signal from the NOR transistor 1 when the input TTL signal is a high level signal. When the input TTL signal is switched from the high level signal to the low level signal, the rising time of the output is delayed and the overall conversion speed is slowed. By simultaneously turning on the CMOS transistor of the NOA gate circuit to be turned on, the PMOS transistor of the speed control section of the speed control circuit is turned on to increase the rise time to increase the overall speed of converting the level. In addition, since the speed control circuit composed of a charge / discharge dedicated PMOS transistor, a constant voltage part, and a speed control part is simply configured, it can be easily used for a conventional level converter.

Claims (5)

제어신호(CS)에 의하여 제어되는 PMOS트랜지스터(PI1)와 NMOS트랜지스터(NI1)와 TTL신호를 입력으로 하는 PMOS트랜지스터(PI2) 및 NMOS트랜지스터(NI2)로 구성된 CMOS트랜지스터로 구성된 노아게이트회로(1)를 구비하고, 상기 노아게이트회로(1)의 출력단자에 노아게이트회로(1)의 노아게이트회로(1)를 구비하고 인버터와 구성된 레벨변환기에 있어서, TTL입력신호에 따라 충방전되는 충방전부(3)와, 상기충방전부(3)의 출력단자에 정전압(VR)을 설정하기 위한 정전압부(4)와, 상기 충방전부(3)의 충방전 전압과 정전압부(4)의 정전압(VR)에 의하여 변환속도가 제어되는 속도제어부(5)로 연결 구성된 레벨변환기.Noah gate circuit (1) consisting of a CMOS transistor consisting of a PMOS transistor (PI1), an NMOS transistor (NI1), and a TTL signal, which are controlled by a control signal (CS), and a PMOS transistor (PI2) and an NMOS transistor (NI2). And a charge / discharge unit configured to include a noa gate circuit (1) of the noa gate circuit (1) at an output terminal of the noagate circuit (1), and to be charged and discharged according to a TTL input signal. 3), the constant voltage unit 4 for setting the constant voltage VR at the output terminal of the charge and discharge unit 3, the charge and discharge voltage of the charge and discharge unit 3 and the constant voltage VR of the constant voltage unit 4 Level converter connected to the speed control unit 5 is controlled by the conversion speed. 제1항에 있어서, 충방전부(3)는 입력단자에 PMOS트랜지스터(PI3)의 게이트단자를 연결하고, 상기PMOS트랜지스터(PI3)의 드레인단자와 소오스단자를 연결하여 구성된 레벨변환기.The level converter according to claim 1, wherein the charge / discharge unit (3) is configured by connecting a gate terminal of a PMOS transistor (PI3) to an input terminal, and a drain terminal and a source terminal of the PMOS transistor (PI3). 제1항에 있어서, 정전압부(4)는, 정전원(Vcc)가 NMOS트랜지스터(NI3)의 게이트와 드레인에 인가되도록 연결하고, 상기 NMOS트랜지스터(NI3)의 소오스단자에 고저항(R)을 연결하여 구성된 레벨변환기.The constant voltage unit 4 is connected so that the electrostatic source Vcc is applied to the gate and the drain of the NMOS transistor NI3, and a high resistance R is applied to the source terminal of the NMOS transistor NI3. Level converter connected by configuration. 제1항에 있어서, 속도제어부(5)는, 충방전부(3)의 충방전 전압과 정전압부(4)의 정전압(VR)에 의하여 온-오프되는 PMOS트랜지스터(PI4)로 구성된 레벨변환기.The level converter according to claim 1, wherein the speed controller (5) comprises a PMOS transistor (PI4) which is turned on and off by the charge and discharge voltage of the charge and discharge unit (3) and the constant voltage (VR) of the constant voltage unit (4). 제3항에 있어서, 정전압부(4)의 고저항(R)은 폴리실리콘이나 아주 작은 크기의 게이트가 상대 접지전압(VSS)과 연결된 PMOS트랜지스터로 구성된 레벨변환기.4. The level converter according to claim 3, wherein the high resistance (R) of the constant voltage section (4) consists of polysilicon or a PMOS transistor whose gate of very small size is connected with a relative ground voltage (VSS).
KR1019890015443A 1989-10-26 1989-10-26 Level shift circuit KR920006251B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019890015443A KR920006251B1 (en) 1989-10-26 1989-10-26 Level shift circuit
JP2047084A JPH03147419A (en) 1989-10-26 1990-02-27 Level converter
GB9004352A GB2238681B (en) 1989-10-26 1990-02-27 A level converter
FR909002441A FR2653951B1 (en) 1989-10-26 1990-02-27 LEVEL CONVERTER.
DE4006144A DE4006144A1 (en) 1989-10-26 1990-02-27 LEVEL CONVERTER

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890015443A KR920006251B1 (en) 1989-10-26 1989-10-26 Level shift circuit

Publications (2)

Publication Number Publication Date
KR910008842A KR910008842A (en) 1991-05-31
KR920006251B1 true KR920006251B1 (en) 1992-08-01

Family

ID=19291059

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890015443A KR920006251B1 (en) 1989-10-26 1989-10-26 Level shift circuit

Country Status (5)

Country Link
JP (1) JPH03147419A (en)
KR (1) KR920006251B1 (en)
DE (1) DE4006144A1 (en)
FR (1) FR2653951B1 (en)
GB (1) GB2238681B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4127212A1 (en) * 1991-08-16 1993-02-18 Licentia Gmbh Logic signal level conversion circuit - uses reference stage to ensure defined level adjustment independent of temp. variations
KR940005509B1 (en) * 1992-02-14 1994-06-20 삼성전자 주식회사 Voltage up inhibition circuit and output buffer circuit with it
JP3038094B2 (en) * 1992-12-24 2000-05-08 三菱電機株式会社 Output circuit of semiconductor integrated circuit device
DE102007005403A1 (en) 2007-02-03 2008-08-07 Man Roland Druckmaschinen Ag Sheet-separating suction device for feeder of sheet printing press, has drive device including stroke length adjusting device for fixing suction position by adjustment of length of stroke of cup along vertical running path
DE202010003265U1 (en) 2010-03-08 2010-05-27 Manroland Ag suction head
DE202011001879U1 (en) 2010-12-16 2011-03-24 Manroland Ag suction device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258272A (en) * 1979-03-19 1981-03-24 National Semiconductor Corporation TTL to CMOS input buffer circuit
JPS5873233A (en) * 1981-10-28 1983-05-02 Nec Corp Semiconductor integrated circuit
JPS58184821A (en) * 1982-03-31 1983-10-28 Fujitsu Ltd Boosting circuit
US4501978A (en) * 1982-11-24 1985-02-26 Rca Corporation Level shift interface circuit
JPS6162230A (en) * 1984-09-04 1986-03-31 Seiko Epson Corp Interface circuit
US4593212A (en) * 1984-12-28 1986-06-03 Motorola, Inc. TTL to CMOS input buffer
JPS61170125A (en) * 1985-01-23 1986-07-31 Oki Electric Ind Co Ltd Output circuit
JPS6213120A (en) * 1985-07-10 1987-01-21 Mitsubishi Electric Corp Semiconductor device
JPS6269719A (en) * 1985-09-24 1987-03-31 Toshiba Corp Level conversion logic circuit
US4689505A (en) * 1986-11-13 1987-08-25 Microelectronics And Computer Technology Corporation High speed bootstrapped CMOS driver

Also Published As

Publication number Publication date
JPH03147419A (en) 1991-06-24
DE4006144C2 (en) 1992-03-05
GB2238681B (en) 1994-03-23
GB2238681A (en) 1991-06-05
FR2653951A1 (en) 1991-05-03
GB9004352D0 (en) 1990-04-25
DE4006144A1 (en) 1991-05-23
FR2653951B1 (en) 1992-02-14
KR910008842A (en) 1991-05-31

Similar Documents

Publication Publication Date Title
US4731553A (en) CMOS output buffer having improved noise characteristics
US4779013A (en) Slew-rate limited output driver having reduced switching noise
US5444396A (en) Level shifting circuit
EP0329285B1 (en) Output buffer
US5488322A (en) Digital interface circuit with dual switching points for increased speed
KR920010819B1 (en) Joutput buffer circuit with level conversion function
KR0130037B1 (en) Semiconductor integrated circuit input buffer
WO1997004528A1 (en) Low noise tri-state output buffer
JPH08501909A (en) System and method for reducing ground bounce in integrated circuit output buffers
US5097148A (en) Integrated circuit buffer with improved drive capability
US4638182A (en) High-level CMOS driver circuit
US6163179A (en) Voltage level transfer
US6559676B1 (en) Output buffer circuit
KR920006251B1 (en) Level shift circuit
JPH09121151A (en) Data output buffer
US4918332A (en) TTL output driver gate configuration
US5160860A (en) Input transition responsive CMOS self-boost circuit
US5118972A (en) BiCMOS gate pull-down circuit
WO1996003738A1 (en) Method for multiplexing video information
KR960016434B1 (en) Output buffer circuit with noise reduction circuit
JP2978302B2 (en) Output buffer circuit
KR19980701819A (en) Low voltage logic circuit
US5051624A (en) High speed level converter to convert a TTL logic signal to a CMOS logic signal
US5831908A (en) Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit
JP2767909B2 (en) Output buffer circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050708

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee