KR920006181B1 - Channel controlling devices of electronic musical instrument - Google Patents

Abstract

The apparatus includes a flip-flop (11) for receiving reset signals from an OR gate (12), and for outputting N-bit signals. A priority encoder (13) selects the highest priority channel to output m- bit signals, and a channel servicing circuit (17) receives the output of the priority encoder (13 to supply its output to a timing control circuit (16). A decoder (15) receives the output of an M-bit latch (14) to supply its output to the OR gate (12), and the OR gate (12) receives reset signals from the timing control circuit (16) to reset the flip-flop (11). With the circuit, the channel service requests are all handled, so that the all channels operates without a sound discontinuity.

Description

Channel controller of electronic musical instrument

1 is a basic block diagram of an electronic musical instrument.

FIG. 2 is a block diagram of a sound source device in FIG.

3 is a conventional channel priority control circuit diagram.

4 is an operation timing diagram in FIG.

5 is a block diagram illustrating a connection state between a channel priority control circuit and an external circuit according to the present invention.

6 is an operation timing diagram in FIG.

* Explanation of symbols for the main parts of the drawings

1: keyboard circuit 2: puff key detection circuit

3: Sound selection table 4: Controller

5: sound source device 6: sound circuit

7 controller interface 8 waveform generator

9: channel priority control circuit 10: priority encoder

11: flip-flop 12: Oagate

13: priority encoder 14: m-bit latch

15 decoder 16 timing control circuit

17: channel service circuit 18: channel request circuit

SP: Speaker

The present invention relates to the processing of a plurality of channels in an electronic musical instrument device, in particular to store the service requests of multiple channels occurring at the same time to service the channels of high priority, and to be suitable for the operation of the services of other channels It relates to a channel control apparatus of the configured electronic instrument.

FIG. 1 is a basic block diagram of an electronic musical instrument that is generally used. The keypress detection circuit 2 to which the keyboard circuit 1 is connected is connected to the controller 4, and the controller 4 to which the music selection table 3 is connected. ) Is connected to the sound source device 5, the sound source device 5 is connected to the sound circuit 6, the sound circuit 6 is a configuration connected to the speaker SP, Figure 2 is the basic of the electronic instrument As a block diagram of the internal configuration of the sound source device 5 in the circuit configuration, the controller 4 is connected to the controller interface in the sound source device 5, and the controller interface 7 is connected to the waveform generator 8 and the channel priority control circuit. The waveform generator 8 connected to 9) and the channel priority control circuit 9 are connected to the acoustic circuit 6.

In FIG. 2, the channel priority control circuit 9 receives N channel (CHO to CHn-1) signals as shown in FIG. 3 to output m bits (DO to Dm-1). It consists of a Priority Encoder (10) for generating the output of the bit (E), the operation state of the configuration described with reference to the timing diagram shown in FIG.

First, in FIG. 1, when the keyboard information pressed from the keyboard circuit 1 and the pressed finger detection circuit 2 is input to the controller 4, the controller 4 provides information on the type of music selected in the music selection table 3; And sends information about the pressed key to the sound source device (5).

Thereafter, the sound source device 5 generates the designated sound using these information, sends the sound to the acoustic circuit 6, amplifies the sound, and outputs the sound through the speaker SP. At this time, the sound source device 5 receives the information such as the presse information and the type of the sound tone input from the controller 4 through the controller interface 7, as shown in Figure 2, the controller interface 7 is a waveform generator ( 8) and the data is sent to the channel priority control circuit 9 for processing, and then a signal is output to the acoustic circuit 6.

That is, the channel priority control circuit 9 of FIG. 3 is a circuit for handling a case where a key is pressed simultaneously or a channel service request from the waveform generator 8 occurs at the same time. It selects the channel with the highest priority among the channel service requests and outputs the channel number with the highest priority.

The circuit configured as described above has a problem in that the number of channels having high priority is output as shown in the operation timing diagram shown in FIG. 4, but at the same time, service requests for other channels are not remembered and lost.

That is, service requests of channels 0 and 1 simultaneously generated at time A in FIG. 4 output channel 0 with "D1DO = OO" at output lines D1 and D0, and channel numbers with high priority at time B and C, respectively. Channels 1 and 0 are output.

On the other hand, since the service request of channel 2 generated at the time point D has no service request of a channel having higher priority than channel 2, the channel 2 number is output as it is. Although the channel with the higher priority is selected, the service request of the channel with the lower priority is ignored, so that the sound related to the channel with the lower priority causes the quality of the sound output by discontinuous service.

Accordingly, the technical configuration of the channel control apparatus according to the present invention which solves the above problems will be described in detail with reference to the accompanying drawings.

를 통해 타이밍 제어회로(16)로 부터 래치용 클럭(LCK)을 인가받고, 출력(LO∼Lm-1)은 디코더(m Line to N Line Decoder)(15)의 입력으로 공급되고, 타이밍 제어회로(16)는 시스템 클럭(0)과 우선순위엔코더(13)로 부터의 출력(E)을 인가받아 신호(TER,LCK)를 출력하며, 출력(TER)은 오에게이트(12)에 입력되는 구성으로서, 상기 구성의 동작 상태 및 작용, 효과를 첨부한 도면에 따라 상세히 설명하면 다음과같다.In FIG. 5, the channel priority control circuit 9 is connected to the external circuits 16, 17, and 18. In other words, the channel signals CHO to CHn to -1 requested from the channel request circuit 18 are input to each set terminal S of the RS flip-flop 11, and m to N lines are supplied to the reset dot R. The output of the decoder 15 which decodes the signal into the decoder 15 is input via the oragate 12, and the outputs FCHO to FCHn-1 of the RS flip-flop 11 are N Line to m Line Encoder 13 Input to the encoder 13, the outputs DO to m-1 of the encoder 13 are supplied to the channel service circuit 17 and input to the m bit latch 14, and other outputs E of the priority encoder 13 are input. ) Is input to the timing control circuit 16, and the m bit latch 14 is a latch enable terminal.

The latch clock LCK is applied from the timing control circuit 16 to the output, and the outputs LO to Lm-1 are supplied to an input of a decoder (m Line to N Line Decoder) 15, and the timing control circuit (16) receives the output (E) from the system clock (0) and the priority encoder 13 and outputs the signals (TER, LCK), the output (TER) is configured to be input to the O gate (12) As follows, the operation state, action, and effect of the configuration will be described in detail with reference to the accompanying drawings.

In FIG. 5, there are N-channel RS-flop flops 11 inside the control circuit 9 in order of channel priority, and each channel CHO to CHn is provided at the set end S of the RS flip-flop 11. Every time a request is made to service -1), a channel request signal is input from the channel request circuit 18, which changes from the state of 1 to the state of 0.

은 0 상태로 변화하며, N개의 플립플롭(11)이 있어서 각각의 플립플롭(11a∼11n)의 출력(FCHO∼FCHn-1)을 입력으로 하는 우선순위 엔코더(13)는 엔코딩된 출력(DO∼Dm-1)을 만들어 낸다.When the signals CHO to CHn-1 are input to the set terminal S of the RS flip-flop 11 in this manner, the inverted output of the RS flip-flop whenever the signal is input.

Is changed to the 0 state, and there are N flip-flops 11, and the priority encoder 13 which inputs the outputs FCHO to FCHn-1 of each of the flip-flops 11a to 11n receives an encoded output DO. To produce Dm-1).

상태가 0을 유지하므로 리셋될때까지 채널 요청회로(18)로부터의 입력신호(CHO∼CHn-1)인 서비스요청정보를 게속 기억하고 있게되며, 상기 RS플럽플롭(11)의 반전출력

을 입력(FCHO∼FCHn-1)으로 하는 우선순위 엔코더(13)는 N개의 입력중 가장 우선순위가 높은 채널을 선택하여 m비트로서 출력(DO∼Dm-1)하고 엔고딩된 출력이 유효할때에만 출력(E)이 0으로 된다. 이후 m비트 래치(14)는 우선순위 엔코더(13)의 출력(DO∼Dm-1)을 입력으로 하여 인에이블단

에 인가되는 타이밍 제어회로(16)의 레치용 클럭(LCK)에 동기되어 상기 엔코더(13)의 출력(DO∼Dm-1)을 기억하고 있으며, 출력(LO∼Lm-1)을 디코더(15)에 공급한다.At this time, RS flip flag (11) keeps inverting output until reset (R) input is input.

Since the state remains 0, the service request information, which is the input signals CHO to CHn-1 from the channel request circuit 18, is continuously stored until reset, and the inverted output of the RS flop flop 11 is kept.

Input encoders (FCHO to FCHn-1) select the highest priority channel among the N inputs, output them as m bits (DO to Dm-1), and the encoded outputs are valid. Only when the output (E) goes to zero. The m-bit latch 14 then uses the outputs DO-Dm-1 of the priority encoder 13 as inputs to enable the stage.

The outputs DO to Dm-1 of the encoder 13 are stored in synchronization with the latch clock LCK of the timing control circuit 16 applied to the decoder 15, and the outputs LO to Lm-1 are decoded from the decoder 15. Supplies).

At this time, the decoder 15 decodes N outputs from m inputs, and is supplied to one input of each OR gate 12, and a timing control circuit is provided to the other input of each of the OR gates 12. Only when the signal TER is supplied from 16 and both inputs of each of the oragates 12a to 12n are " 0 ", the outputs RO to Rn-1 of the corresponding gates become 0 and each RS flip-flop 11a -11n) to the reset stage R.

In addition, the timing control circuit 16 receives the system clock φ and the output E of the priority encoder 13, and outputs the latch enable clock LCK to the m-bit latch 14, and the channel service circuit. 17 causes the signal TER to be zeroed through the timing control circuit 16 after the service for the channel is completed.

This operation state is described with reference to FIG. 6 by way of example. In FIG. 6, when the signals CHO and CH1 go to 0 at the same time as the time E from the channel request circuit 18, the service requests for the channel 0 and the channel 1 are output of the RS flip-flops 11a and 11b. (FCHO, FCH1) are all 0, and the priority encoder 13 determines that the smaller channel number among the two inputs (FCHO, FCH1) has a higher priority, and the output (DO to Dm-1) is assigned to channel 0. Binary is output in m bits.

On the other hand, the output E of the priority encoder 13 becomes 0 when at least one of the inputs FCHO to FCHn-1 is 0, and this signal E is supplied to the timing control circuit l6 to output the encoder. The latch clock (LCK) is output only when (E) is zero.

Therefore, when the clock LCK is output from the timing control circuit 16, the m-bit latch 14 latches the data DO to Dm-1 indicating the channel number 0 to output the outputs LO to Lm-1 to the decoder 15. The decoder 15 decodes the outputs LO to Lm-1 of the m-bit latch 14 to zero one of the corresponding output lines, and at the same time, the channel service circuit 17 services the channel 0. Signal is sent to the timing control circuit 16 at the end point F, so that the signal TER becomes zero. Therefore, the output Ro of the oragate 12a becomes zero, thereby resetting the RS flip-flop 11a (R). Return the output FCHO to the state 1, and at the same time, the priority encoder 13 outputs channel number 1 since the state of "FCH1 = 0" at this point.

The channel service request generated at the same time can be serviced immediately after the service of the high priority channel is completed without ignoring the low priority service request due to the memory function of the RS flip-flop 11. The service request of channel 2 generated at time G can be serviced immediately because there is no service request of a higher channel.

As described above, the channel control apparatus of the electronic musical instrument according to the present invention can improve the quality of the musical sound by processing all channel service requests generated at the same time so that the sound corresponding to each channel can be faithfully generated without interruption, and can be implemented with a simple configuration. As a result, the integrated circuit can be easily manufactured at low cost.

Claims (1)

It is set S by the channel signals CHO to CHn-1 requested from the channel request circuit 18, and receives the reset signals RO to Rn-1 from the oragate 12.

Receive the N-bit signals FCHO to FCHn-1 and the N-bit signals FCHO to HCHn-1 from the flip-flop 11 to receive the highest priority channel. A priority encoder 13 which selects and outputs m bits at the same time (DO to Dm-1) and outputs a validity signal E of an encoded output, and an output (DO to Dm−) of the priority encoder 13. 1) receives a signal E from the channel service circuit 17 for controlling the reset signal TER output from the timing control circuit 16 and the priority encoder 13, and sets the clock LCK to m. The timing control circuit 16 outputs to the bit latch 14 and outputs the reset signal TER by the channel service circuit 17, and the clock LCK is applied from the timing control circuit 16 to receive priority data. The m-bit latch 14 which latches (DO to Dm-1) and outputs (LO to Lm-1) and the output (LO to Lm-1) of the m-bit latch 14 are decoded. The decoder 15 outputs to the agate 12 and the reset signal TER from the timing control circuit 16 that receives the output of the decoder 15 and the system clock. An electronic instrument channel control apparatus comprising an orifice (12) for resetting (11) to process all channel service requests generated at the same time.

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