KR920005326A - Noise prevention method of semiconductor device - Google Patents

Noise prevention method of semiconductor device Download PDF

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Publication number
KR920005326A
KR920005326A KR1019900012326A KR900012326A KR920005326A KR 920005326 A KR920005326 A KR 920005326A KR 1019900012326 A KR1019900012326 A KR 1019900012326A KR 900012326 A KR900012326 A KR 900012326A KR 920005326 A KR920005326 A KR 920005326A
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KR
South Korea
Prior art keywords
semiconductor device
film
primary
conductive material
prevention method
Prior art date
Application number
KR1019900012326A
Other languages
Korean (ko)
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KR930001417B1 (en
Inventor
윤욱현
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900012326A priority Critical patent/KR930001417B1/en
Publication of KR920005326A publication Critical patent/KR920005326A/en
Application granted granted Critical
Publication of KR930001417B1 publication Critical patent/KR930001417B1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Abstract

내용 없음.No content.

Description

반도체 소자의 노이즈 방지방법Noise prevention method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1a도는 종래의 구조 단면도, 제1b도는종래의 구성도.Figure 1a is a conventional structural cross-sectional view, Figure 1b is a conventional configuration diagram.

제2도는 본 발명의 공정 단면도.2 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 산화막 2 : 메탈1: oxide film 2: metal

3 : 질화막3: nitride film

Claims (4)

칩의 보호막 형성공정에 있어서, 이중보호막인 1차 및 2차 보호막 사이에 전도성 물질막을 추가로 형성하고 이 전도성 물질막을 그라운드시켜서 칩의 내, 외부로부터 노이즈가 방지되도록 함을 특징으로 하는 반도체 소자의 노이즈 방지방법.In the process of forming a protective film of a chip, the semiconductor device, characterized in that a conductive material film is further formed between the primary and secondary protective films, which are double protective films, and the conductive material film is grounded to prevent noise from inside and outside the chip. How to avoid noise. 제1항에 있어서, 상기 1차 및 2차 보호막은 각각 산화막과 질화막으로 형성함을 특징으로 하는 반도체소자의 노이즈방지방법.The method of claim 1, wherein the primary and secondary protective films are formed of an oxide film and a nitride film, respectively. 제1항에 있어서, 전도성 물질막은 메탈, 폴리, 폴리사이드중 하나로 형성함을 특징으로 하는 반도체 소자의 노이즈방지방법.The method of claim 1, wherein the conductive material layer is formed of one of metal, poly, and polyside. 제2항에 있어서, 1차 보호막인 산화막의 두께는 약1000Å-2000Å의 두께로 형성함을 특징으로 하는 반도체소자의 노이즈방지방법.The method of preventing noise of a semiconductor device according to claim 2, wherein the thickness of the oxide film which is a primary protective film is formed to a thickness of about 1000 kPa-2000 kPa. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900012326A 1990-08-10 1990-08-10 Protect of nose for semiconductor device KR930001417B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900012326A KR930001417B1 (en) 1990-08-10 1990-08-10 Protect of nose for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900012326A KR930001417B1 (en) 1990-08-10 1990-08-10 Protect of nose for semiconductor device

Publications (2)

Publication Number Publication Date
KR920005326A true KR920005326A (en) 1992-03-28
KR930001417B1 KR930001417B1 (en) 1993-02-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900012326A KR930001417B1 (en) 1990-08-10 1990-08-10 Protect of nose for semiconductor device

Country Status (1)

Country Link
KR (1) KR930001417B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363983B1 (en) * 1994-11-22 2003-02-11 가부시끼가이샤 히다치 세이사꾸쇼 Semiconductor integrated circuit
KR100366137B1 (en) * 1994-11-04 2003-04-11 소니 일렉트로닉스 인코포레이티드 Internal Clock Signal Generation Method and Device
KR100439831B1 (en) * 1997-06-05 2004-10-26 삼성전자주식회사 Semiconductor device restraining permeability of alpha particles using heavily doped layer or metal film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366137B1 (en) * 1994-11-04 2003-04-11 소니 일렉트로닉스 인코포레이티드 Internal Clock Signal Generation Method and Device
KR100363983B1 (en) * 1994-11-22 2003-02-11 가부시끼가이샤 히다치 세이사꾸쇼 Semiconductor integrated circuit
KR100439831B1 (en) * 1997-06-05 2004-10-26 삼성전자주식회사 Semiconductor device restraining permeability of alpha particles using heavily doped layer or metal film

Also Published As

Publication number Publication date
KR930001417B1 (en) 1993-02-27

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