KR920005134B1 - Common channel signalling system - Google Patents

Abstract

The realization method of signal link functional scheduler includes the three steps: the first step comprising a scheduler which exchanges the information through a buffer and signal link function module, the second step comprising a processor executing the partially processed input data, the third step gining proper output after executing the second step and executing the signal link function module.

Description

Implementation method of signal link function scheduler of common line signal device

1 is a hierarchical structure diagram of the CCITT NO.7 signaling protocol.

2 is a diagram illustrating a module configuration to which a processor scheduler is applied and an association between modules.

Figure 3 shows the number of module states and functions.

4 is a form of internal processing message and status buffer.

5 is a state transition diagram of a processor.

6 is a flow diagram for a method of processor scheduling.

7 is a flow diagram of a processor scheduler.

* Explanation of symbols for main parts of the drawings

LSC: Link state control function IAC: Initial synchronous control function

POC: Processor idle state control function TXC: Transmission control function

RXC: Receive Control Function AERM: Initial Sync Error Monitoring Function

SUERM: Signal unit error monitoring function COC: Reception congestion control function

RAIN: Speed matching device input interface control function

RAOUT: Speed matching device output interface control function

STNIN: Signal network input interface control function

STNOUT: Signal network output interface control function

TIM: Timer Handling Function

The present invention relates to a method of implementing a scheduler unit applied to a signal link function of a NO.7 common line signaling method for providing a signal required for a call connection procedure in an electronic switch.

It is an object of the present invention to implement a modularity, reliability, flexibility, and more particularly, a scheduler with improved signal link function and a signal generated by the function more efficiently than the conventional method. In addition, the present invention has an object to improve the table search and memory utilization by efficiently managing the lookup table.

The signal link function should follow the CCITT Recommendation, and design the signal link function to improve the efficiency of the central processing unit (CPU) in order to perform the real-time processing on the signal message generated in each module and to minimize the processor processing time. . To this end, the processor scheduler unit is designed in a first-in first-out (FIFO) scheduler according to a state transition.

In addition, it is easy to add, delete, or change the function, so that the signal link function is modularized and the independence between each module is guaranteed.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a hierarchical diagram of common line signaling method No. 7 to which the present invention is applied, and the signal link function must process signals inputted from the signal network function and the signal data link function and signals generated within itself. The processor scheduler has a function of selecting a processor to be serviced by the CPU among these signals.

2 is a diagram illustrating the configuration of modules to which the present invention is applied and a diagram of linkage between modules. That is, the processor to be executed by the processor scheduler of the present invention is generated in association with each module of the present invention.

In Figure 2, LSC is link state control, IAC is initial sync control, POC is processor idle control, TXC is transmit control, RXC is receive control, AERM is initial sync error monitoring. Function, SUERM for signal unit error monitoring, COC for receive congestion control, RAIN for speed matcher input interface control, RAOUT for speed matcher output interface control, STNIN for signal network input interface control SINOUT represents the signal network output interface control function and TIM represents the timer handling function.

FIG. 3 shows the number of internal states and the number of functions for each module in FIG. 2. The processor in the signal link function (also defined as TASK) is divided into each function of the corresponding module in one module. Functions are subdivided by the number of states in this figure.

In the method of selecting the granular processors in the signal link scheduler, the modules and the processors defined according to the internal state of the module are prepared in a table form, and the messages inputted to the FIFO are analyzed to combine the states of the modules to select the processors. do. In other words, the processor table defined by the module of FIG. 2 and the state of FIG. 3 consists of secondary matrix data searched to select a processor to be serviced by the CPU.

Figure 4 shows the format of the internal process (Inter Process Message) and the status buffer in each module for the communication and data exchange between the modules. The internal message is the module function (8bits), data presence (1bit) and data (7bit). Etc., and the status buffer should contain the state (8bit) of the module. When a message defining a processor generated between modules is ready to the FIFO in the form of FIG. 4, the scheduler allocates the service of the CPU to retrieve the waiting messages in turn, analyzes them, and combines the module and the status buffer. The next processor table is searched to activate the processor.

5 illustrates a general state transition of the processor scheduler, and each processor transitions to four states such as Dormant, Ready, Running, and Waiting. The processor in the signal link function state becomes a latent state and when it is created and stored in the FIFO, the processor becomes ready state. When the scheduler analyzes, discovers, and starts a ready processor, it starts or activates and terminates or waits. In addition, the processor, which has been waited by the wait, is driven by a timer and executed again.

FIG. 6 is a diagram illustrating a method of scheduling a processor scheduler, and is specifically illustrated in connection with the signal link function of FIG. 5. The processor output from the signal link function accepts this as an input from the scheduler unit and waits for the FIFO to be ready. The scheduler activates the ready-to-run processors without any priorities to ensure signal rejection of the shared area between processors in each module of the signal link function and to minimize CPU overload as much as possible. The signal link function receives the processor in the running state and processes the processor.

In this way, the processor scheduler unit has a function of selecting one processor to receive the service of the CPU from the various processors generated by the signal link function. In other words, the processor scheduler is a dispatcher that improves the real-time processing capability. To do this, the signal linker module and data are included in an internal message and stored in the FIFO. Next, the processor is most efficiently searched and the processor is executed.

7 is a flowchart of a processor scheduler unit, and describes an efficient table searching method.

Once the services of the CPU are assigned to the processor scheduler, the timers (T1-T7) defined in CCITT Recommendation Q.703 are searched for time out for background processing and the status of each timer is checked. After storing for use in the signal link function, the FIFO is searched for the presence of a standby processor, and if present, the internal message is taken and analyzed.

If the internal message determines whether there is exchange data between processors, the exchange data is stored separately and this part is deleted.

The processor searches the table to calculate the processor to be executed in this analysis step. To improve the scheduler's real-time and storage efficiency, the table is created by associating the module with the number of states of the module. First, in case of the module related to the signal network output interface function, since there is one spare regardless of the state, if the direct message (16bits) is moved to 6bit right, it becomes the table relative address (16bit) of the corresponding processor. The following is a module related to link state control function, so it can be represented as 3 bits because there are 7 states. Therefore, if the message is shifted 4 bits to the right and the corresponding status buffer (8 bits) is shifted 1 bit to the left, it becomes the relative address of the processor table. In the case of the initial synchronous control function module, since the number of states is 4, it can be represented by 2 bits. Therefore, the message can be combined by moving 5 bits to the right. In the case of the processor idle state control function, since there are four states, it is the same as the initial synchronous control function module.

In the case of modules related to the remaining functions, the status can be represented by 1 bit, so if the message is shifted 6 bits to the right and 1 bit to the left (since it is the relative address word size), it becomes the table relative address of the corresponding processor.

When the table relative address of the processor is calculated as above, the scheduler executes the processor with the exchange data on the table corresponding to the relative address.

According to the present invention, the signal link function and the signal generated by the function can be processed more efficiently, and the search table can be effectively managed to improve the table search and the efficient use of the memory.

Claims (3)

A first step consisting of a signal link function module and a scheduler unit for exchanging information through a buffer, a second step of defining a processor to process the input partly if there is an input to the buffer of the first step, and And a third step of performing the signal link function module with an appropriate output after performing the second step. The signal link scheduler of claim 1, wherein the second step includes defining a two-dimensional matrix according to a corresponding function of the signal link function module and each function state to create the processor table. How to implement the feature. The function of the signal link scheduler of claim 2, wherein the second step further comprises searching the processor table by combining the data input in the first step and the state of the corresponding module function. How to implement.

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