KR920004402Y1 - Blanking circuit for tv - Google Patents
Blanking circuit for tv Download PDFInfo
- Publication number
- KR920004402Y1 KR920004402Y1 KR2019860015190U KR860015190U KR920004402Y1 KR 920004402 Y1 KR920004402 Y1 KR 920004402Y1 KR 2019860015190 U KR2019860015190 U KR 2019860015190U KR 860015190 U KR860015190 U KR 860015190U KR 920004402 Y1 KR920004402 Y1 KR 920004402Y1
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- KR
- South Korea
- Prior art keywords
- resistor
- transistor
- crt
- input terminal
- blanking circuit
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/24—Blanking circuits
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
내용 없음.No content.
Description
제 1 도는 본 고안의 귀선소거회로도.1 is a return cancellation circuit of the present invention.
제 2 도 및 제 3 도는 제 1 도 각부의 파형도.2 and 3 are waveform diagrams of respective parts of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
R1-R4: 저항 VR1: 가변저항R 1 -R 4 : Resistance VR 1 : Variable resistor
TR1: 트랜지스터 D1: 다이오드TR 1 : Transistor D 1 : Diode
CRT : 브라운관CRT: CRT
본 고안은 귀선소거회로에 관한 것으로, 특히 콤포지트모니터(composite monitor)에서 화면의 휘도를 높였을 경우에도 귀선이 나타나지 않게하여 항상 선명한 화면을 나타낼 수 있게한 귀선소거회로에 관한 것이다.The present invention relates to a blanking circuit, and more particularly, to a blanking circuit that makes it possible to display a clear screen at all times even when the brightness of the screen is increased in a composite monitor.
종래의 경우에는 모니터 주위가 밝을 경우 화면의 휘도를 높이게 되면 화면상에 수직, 수평 귀선이 나타나게 되어 화면이 눈에 거슬리게 되는 결점이 있었다.In the related art, when the brightness of the screen is bright, when the brightness of the screen is increased, vertical and horizontal retraces appear on the screen, and the screen is unobtrusive.
본 고안은 이와같은 종래의 결점을 감안하여, 수직, 수평펄스를 이용하여, 브라운관의 제어그리드에 인가되는 전압을 제어해줌으로써 휘도를 높였을때에도 귀선이 보이지 않도록 안출한 것으로, 이를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention, in view of such a conventional drawback, by using a vertical, horizontal pulse, by controlling the voltage applied to the control grid of the CRT, so that no retracement is visible even when the brightness is increased, it is attached to the accompanying drawings Detailed description with reference to the following.
제 1 도는 본 고안의 귀선소거회로도로서, 이에 도시한 바와같이, 수직펄스입력단자(VP)를 저항(R1) 및 다이오드(D1)를 통해 저항(R3) 및 트랜지스터(TR1)의 베이스에 공통접속함과 아울러 그 접속점에 수평펄스입력단자(HP)를 저항(R2)을 통해 접속하며, 플라이백트랜스(FBT)의 출력측을 저항(R4)을 통해 그 트랜지스터(TR1)의 콜렉터에 접속함과 아울러 콘덴서(C1)를 통해 브라운관(CRT)의 제어그리드(G1) 및 휘도조정용 가변저항(VR1)에 접속하여 구성한 것으로, 이와같이 구성한 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.FIG. 1 is a blanking circuit diagram of the present invention, and as shown therein, a vertical pulse input terminal VP is connected to a resistor R 3 and a transistor TR 1 through a resistor R 1 and a diode D 1 . In addition to the common connection to the base, the horizontal pulse input terminal HP is connected to the connection point through the resistor R 2 , and the output side of the flyback transformer FBT is connected to the transistor TR 1 through the resistor R 4 . It is configured by connecting to the collector of and connected to the control grid (G 1 ) of the CRT and the variable resistor (VR 1 ) for brightness adjustment through the capacitor (C 1 ). The explanation is as follows.
수직펄스입력단자(VP)에 제 2a 도에 도시한 바와같은 수직펄스가 입력되면, 이 입력신호는 저항(R1) 및 다이오드(D1)를 통해 트랜지스터(TR1)의 베이스에 인가되며, 이때 그 베이스에 인가되는 전압은로서 주어지게 되고(VVP: 수직출력전압), 이에 따라 트랜지스터(TR1)가 온되어 플라이백트랜스(FBT)로 부터의 전원이 트랜지스터(TR1)를 통해 접지로 흐르게 되므로 그의 콜렉터에는 제 2b 도에 도시한 바와같이 저전위 신호가 출력되고, 이 저전위 신호가 브라운관(CRT)의 제어그리드(G1)에 인가됨에 따라 가변저항(VR1)로 휘도를 밝게 해도 귀선이 나타나지 않게된다.When the vertical pulse as shown in FIG. 2A is input to the vertical pulse input terminal VP, the input signal is applied to the base of the transistor TR 1 through the resistor R 1 and the diode D 1 . At this time, the voltage applied to the base (V VP : vertical output voltage), and accordingly, transistor TR1 is turned on so that power from flyback transformer FBT flows through transistor TR 1 to ground, so that the collector of FIG. As shown in FIG. 2, a low potential signal is output, and as the low potential signal is applied to the control grid G 1 of the CRT, the retrace does not appear even if the luminance is brightened by the variable resistor VR 1 .
또한 수평펄스입력단자(HP)에 제 3a 도에 도시한 바와같은 수평펄스가 입력되면, 이 입력신호는 저항(R2)을 통해 트랜지스터(TR1)의 베이스에 인가되며, 이때 그 베이스에 인가되는 전압은로서 주어지게 되고(VHP: 수평출력전압), 이에따라 트랜지스터(TR1)가 온되어 플라이백트랜스(FBT)로부터의 전원이 그 트랜지스터(TR1)를 통해 접지로 흐르게 되므로 그의 콜렉터에 제 3b 도에 도시한 바와같이 저전위 신호가 출력되며, 이 저전위 신호가 브라운관(CRT)의 제어그리드(G1)에 인가됨에 따라 가변저항(VR1)으로 휘도를 밝게 해도 귀선이 나타나지 않게 된다.In addition, when the horizontal pulse as shown in FIG. 3A is input to the horizontal pulse input terminal HP, the input signal is applied to the base of the transistor TR 1 through the resistor R 2 , and then to the base. Voltage (V HP : horizontal output voltage), and accordingly, transistor TR 1 is turned on so that power from flyback transformer FBT flows through the transistor TR 1 to ground, so that FIG. As shown in FIG. 2, a low potential signal is output, and as the low potential signal is applied to the control grid G 1 of the CRT, the retrace does not appear even though the luminance is brightened by the variable resistor VR 1 .
이상에서 설명한 바와같이 본 고안은 수직 및 수평펄스를 이용하여 브라운관의 제어그리드에 인가되는 휘도 조정전원을 제어해줌으로써 휘도를 밝게 해도 귀선이 소거되어 선명한 화면을 나타낼 수 있는 효과가 있게된다.As described above, the present invention controls the luminance adjustment power applied to the control grid of the CRT by using vertical and horizontal pulses, so that the luminance can be cleared so that a clear screen can be displayed.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860015190U KR920004402Y1 (en) | 1986-10-04 | 1986-10-04 | Blanking circuit for tv |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860015190U KR920004402Y1 (en) | 1986-10-04 | 1986-10-04 | Blanking circuit for tv |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR880008915U KR880008915U (en) | 1988-06-30 |
| KR920004402Y1 true KR920004402Y1 (en) | 1992-06-29 |
Family
ID=19256071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019860015190U KR920004402Y1 (en) | 1986-10-04 | 1986-10-04 | Blanking circuit for tv |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR920004402Y1 (en) |
-
1986
- 1986-10-04 KR KR2019860015190U patent/KR920004402Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR880008915U (en) | 1988-06-30 |
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