KR920004392B1 - Video display adaptor - Google Patents

Abstract

The adaptor includes a graphic system processor (45) for graphically processing inputted data by receiving the data from a personal computer (10). A system memory (65) stores system programs, and a frame memory (75) stores picture data to display it on the screen. A memory interface section (55) interfaces so as for control commands and data to be stored in the system memory (65) and the frame memory (75). A video output section (95) processes the output data of the frame memory (75) in accordance with the control commands, and video timing generator (85) supplies control timing signals to the components (45)(75)(95). With the apparatus, the resolving power and the prequency easily varied.

Description

Video display adapter

1 is a conventional circuit diagram.

2 is a block diagram according to the present invention.

3 (a)-(e) are detailed circuit diagrams of each part of FIG. 2 according to the present invention.

TECHNICAL FIELD The present invention relates to video display devices, and more particularly, to high resolution video display adapters for desktop and CAD / CAM. In general, it is well known that video display devices for desktop publishing and CAD / CAM should have high resolution. However, although high resolution display devices are not widely available yet, a few companies have used chips dedicated to processing graphics, each of which executes specific software. Referring to Fig. 1, a conventional technique has been described. The command or data input from the personal computer 10 is analyzed by internal timing and program analysis of the display data processing unit 30 through the personal computer interface unit 20. And store the data in the memory unit 40, and output the data stored in the memory unit 40 after the output data is processed by the output processing unit 50 by the signal output from the display data processing unit 30. However, in the related art, since a dedicated chip of the display data processing unit 30 designed for a special purpose is used, there is no compatibility with other programs, and the timing processing unit is set inside the display data processing unit 30 to change the resolution of the screen. And there is a problem that the frequency change is not free and difficult to match the characteristics of the monitor, and the complexity of the dedicated chip makes it difficult to design freely from other companies, and the design of the enhanced video board is difficult to be widely used. there was.

Accordingly, an object of the present invention is to provide a circuit that can easily change resolution and frequency and to design a video board having various functions without changing a basic circuit configuration by changing an internal register using a graphics system processor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram according to the present invention, which has a personal computer interface 20 for facilitating mutual transmission of data and commands input and output from the personal computer 10. As shown in FIG. The video board is a peripheral device of the personal computer 10, and main memory transmits the results and commands of the processing portion in the personal computer 10 to the monitor for display on the screen. Therefore, a personal computer interface 20 for separating and buffering the command outputted from the personal computer 10 or the analyzed data in accordance with this operation is required. The personal computer interface unit 20 has a programmable logic unit therein and is configured to output a specific signal in accordance with the address and data output from the personal computer 10.

A graphics system processor 45 having a function of controlling a memory, a screen, a timing chart, a graphics processor, and graphics processing by data input from the personal computer 10; and a system memory having a system program embedded therein ( 65, a frame memory 75 storing screen display data in frame units, and control commands and data output from the graphics system processor 45 are stored in the system memory 65 and frame memory 75. FIG. A memory interface unit 55 for interfacing so that the data can be well stored in the video memory, a video output unit 95 for outputting the output data of the frame memory 75 according to a control according to the resolution and the number of colors, and the graphic; Video for supplying control timing signals to the system processor 45, the frame memory 75, and the video output unit 95 It consists of a false timing generator 85.

FIG. 3A is a detailed circuit diagram of the memory interface unit 55 of FIG. 2, and includes a latch 501 for latching data input and output to the graphics system processor 45 and a PAL logic for the data output from the graphics system processor 45. The decoder 503 decodes the signal to generate a control signal, and the buffer 502 buffers data input / output between the latch 501 and the system memory 65 and the frame memory 75.

FIG. 3B is a detailed circuit diagram of the personal computer interface unit 20 of FIG. 2, which includes bus transceivers 201 and 202 for buffering address, data, and command data input and output from the personal computer 10, and the personal computer 10. FIG. The PAL 201 generates a control signal according to decoding the address signal outputted to the bus transceivers 201 and 202 by the control signal outputted from the PAL 201 and the address signal passing through the bus transceivers 201 and 202. It consists of an EPROM 204 for generating program data.

FIG. 3C is a detailed circuit diagram of the graphic system processor 45 of FIG. 2, and is provided from the host interface 20 to the graphic processor GP, the memory control circuit MC, the screen control circuit SC, and the timing control circuit TC. It consists of.

FIG. 3D is a detailed circuit diagram of the video timing generator 85 of FIG. 2, configured to generate a clock by inputting a generation signal of the oscillator 801 to the signal level interface circuit 802 to form a signal to generate a clock in the clock generator 803. It is.

FIG. 3E or FIG. 2 is a detailed circuit diagram of the video output unit 905. Flip-flops 901 and 902 for latching data output from the frame memory 75 and control signals generated by the video timing generator 85. FIG. The multiplexers 903 and 904 for selecting data of the number of colors output from the flip-flops 901 and 902 and the control signals generated by the video timing generator 85 according to the multiplexers And a color palette 905 for receiving the output data of the 903 and 604 and performing color processing to output the data.

Therefore, a specific embodiment of the present invention will be described in detail with reference to Figs. 2 to 3, when the results and commands of the processing portion in the personal computer 10 are transmitted to the monitor and displayed on the screen, the video board alone commands. Since it is impossible to perform, the personal computer interface 20 which analyzes a command or data input from the personal computer 10 or separates a signal corresponding thereto is processed by the graphic system processor 45, which is required. 3b is the same as help. Data generated by the personal computer 10 and buffered by the address signal bus transceivers 201 and 202 and input to the PAL 203 and the EPROM 204, the PAL 203 requires the control of the graphics system processor 45. A signal is generated and control program data is generated in the graphics system processor 45 in the EPROM 204.

The data output from the personal computer interface unit 20 is processed according to the timing change and resolution of the graphics processor GP in the graphics system processor 45 as shown in FIG. 3C. The screen is controlled by the timing control circuit TC. The graphic data is processed by the control of the control circuit SC.

The data processed by the graphic system control circuit 45 is applied to the memory interface unit 55 of FIG. 3A, and according to the decoding of the signal input from the decoder 503, the system memory 65 and the frame memory 75 are separated. Generates a chip enable and read / write control signal, latches the output data of the graphic system control circuit 45 in the latch 501, and stores data to be displayed on the screen in the frame memory 75 through the buffer 502. do. The frame memory 75 uses video memory at high resolution in relation to speed and data transmission. When the signal generated by the oscillator 801 is inputted to the clock generator 803 by shaping the level from the signal level interface circuit 802 as shown in the 3D diagram, the video timing generator 85 receives the graphic system processor 45 and the frame memory. (75) A desired timing signal obtained by dividing and combining each timing signal required for the video output unit 95 is generated.

In the frame memory 75, data output from the frame memory 75 according to the generator control signal from the video timing generator 85 is latched from the flip-flops 901 and 902 as shown in the 3e diagram and under the control of the control stage 900. In the multiplexers 903 and 904, the output data of the flip-flops 901 and 902 may be determined according to the number of colors and input to the color palette 905 to obtain a desired color of 16 or 256.

As described above, it is possible to easily add or reduce the memory part when changing the resolution, and it is possible to easily change the supply clock of the video timing part or change the internal register value of the graphic system processor when changing the frequency, and thus various kinds without changing the basic configuration. Has the advantage of designing a video card.

Claims (1)

A video adapter card of a video display device connected to a personal computer 10 and a personal computer interface unit 20, the personal computer 10 having a function of controlling a memory, a screen, a timing chart, and a graphics processor. A graphics system processor 45 for processing graphics by data input from the system, a system memory 65 incorporating a system program, a frame memory 75 storing display data on a screen in units of frames, A memory interface unit 55 for interfacing control commands and data output from the graphic system processor 45 to be stored in the system memory 65 and the frame memory 75 and the frame memory 75 of the frame memory 75. Video output that changes the output data according to the control according to the resolution and the number of colors. A video display adapter, characterized by consisting of a (95), and the graphics system processor 45, a frame memory 75, a video output unit 95. Video timing generator 85 for supplying a control signal to the timing.

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