KR920004374B1 - Phase locked loop circuit for compensating frequency deviation of mobile telephone - Google Patents

Abstract

The frequency synthesizer uses a phase locked loop (PLL) circuit utilized to compensate the frequency of supperheterodyne wireless equipment. The frequency synthesizer matches exactly the first and the second intermediate frequency even when the received frequency is out of joint. The synthesizer includes a voltage controlled temperature compensating oscillator (21) for receiving DC voltage corresponding to frequency error of the second intermidiate frequency a frequency divider (51) for dividing the frequency of the oscillated signal, a pre-scaler (11) for lowering the frequency of a voltge controlled oscillator (17), a phase comparator (13) connected to a programmable counter and the frequency divider (15), and a first PLL circuit (20) for filtering the output signal of the phase comparator (13) and for applying to the VCO (17).

Description

Frequency synthesizer

1 is a block diagram of a prior art.

2 is a block diagram of the present invention.

* Explanation of symbols for main parts of the drawings

2, 5: Mixer 11: Prescaler

12: programmable counter 13: phase comparator

14 low pass filter 15 reference clock divider

17: voltage controlled oscillator 21: reference oscillator for voltage controlled temperature compensation

31: Programmable Counter 32: Low Pass Filter

33: phase comparator 34: reference clock divider

35: reference oscillator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer using a phase locked loop (PLL) circuit used for frequency correction of various wireless devices such as super heterodyne type automobile telephones and wireless telephones.

The conventional frequency synthesizer lowers the signal from the voltage controlled oscillator (VCD) 17 to the operable frequency of the programmable counter 12 in the prescaler 11 as shown in FIG. The phase comparator 13 compares two phase differences of the signal divided by the reference force divider 15 that divides the signal divided by the signal from the temperature compensation reference oscillator (TCXD) 16 with the phase comparator 13, and corresponds to the phase difference. After the high frequency component is removed from the low pass filter (LPF) 14 by adjusting the oscillation frequency of the voltage controlled oscillator (VCO) 17, the output signal is outputted by the primary mixer 2 to the antenna. Is mixed with the received signal from the RF low noise amplifier 1 to produce an intermediate frequency and then input to the secondary mixer 5 via filters and intermediate frequency amplifiers 3 and 4. In the secondary mixer 5, the input signal is mixed with the output signal of the secondary local oscillator 9 to produce a second intermediate frequency, and then the bandpass filter 6, the secondary intermediate frequency amplifier 7, In the configuration diagram leading to the demodulator 8, when the signal frequency received from the antenna is shifted, the first intermediate frequency after passing through the primary mixer 2 is shifted, so that the band pass filter BPF having a narrow bandwidth of the next stage is Due to the misalignment, there is a problem that the adjacent channel selectivity and the demodulated audio signal are affected.

An object of the present invention is to solve the above problems, and even when the reception frequency is shifted, the first and second intermediate frequencies can be exactly matched, and the demodulation characteristics due to the shift of the center frequency of the band pass filter of the first and second intermediate frequencies are different. To provide a frequency synthesizer with no effect.

The present invention provides a frequency synthesizer for forming a first intermediate frequency through a primary mixer and a second intermediate frequency through a secondary mixer to achieve the above object, at the second intermediate frequency. A reference oscillator for voltage controlled temperature compensation for inputting a DC voltage corresponding to a frequency error, a reference clock divider for dividing an output from the oscillator, a voltage controlled oscillator, a prescaler connected to the voltage controlled oscillator, a programmable counter connected to the prescaler, And a primary PLL circuit including a phase comparator connected to the programmable counter, a reference clock divider, and a low pass filter for filtering the output of the phase comparator and applying the voltage to the voltage controlled oscillator, the output of the primary PLL circuit. Is applied to the primary mixer.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic diagram of the present invention, in which the same reference numerals are used for the same parts as in FIG. 2, 20 is the first PLL circuit, 30 is the second PLL circuit, 21 is the reference oscillator for voltage controlled temperature compensation, 31 programmable counter, 32 is the low pass filter, 33 is the phase comparator, 34 Denotes a reference clock divider and 35 denotes a reference oscillator.

The first PLL circuit 20 includes a voltage controlled temperature compensating reference oscillator (VCTCXO) 21, and the output of the voltage controlled oscillator VCO frequency-adjusted by the first PLL circuit 20 is a first output. The second and second intermediate frequencies output after passing through the second and second mixers 2 and 5 and the band pass filter 6 are programmed in the second PLL circuit 30 using another reference oscillator 35 ( 31), the divided signal and the signal divided by the reference clock divider 34 are compared in the phase comparator 33, and the voltage difference corresponding to the phase difference is passed through the low pass filter to compensate for the voltage control temperature. By applying to the voltage control terminal of the reference oscillator 21, the frequency of the reference oscillator 21 for voltage control temperature compensation, which is the reference oscillator of the first PLL circuit, is corrected. As a result, the primary and secondary mixers 2, The intermediate frequency passed through 5) can be precisely controlled.

In other words, in the present invention, instead of the temperature-controlled reference oscillator (TCXO) in the conventional PLL circuit, the voltage-controlled temperature-compensated reference oscillator (VCTCXO) 21 is used to receive the looped output of the local end of the primary mixer 2. DC voltage corresponding to the frequency error up to the secondary intermediate frequency by inputting to the port and configuring the PLL circuit 30 using another reference oscillator 35 for the secondary intermediate frequency passed through the secondary mixer 5. Is inputted to the reference oscillator 21 for voltage controlled temperature compensation to correct the frequency so that the first and second intermediate frequencies of the mixer output can be accurately matched even when the frequency received from the antenna is shifted.

According to the present invention, even when the reception frequency is shifted, the first and second intermediate frequencies can be accurately matched, so that the adjacent channel selectivity characteristics of the terminal are stabilized, and the intermediate frequencies of the first and second intermediate frequency bandpass filters are shifted. The influence of the demodulation characteristic due to this can be eliminated.

Claims (3)

In a frequency synthesizer which forms a first intermediate frequency through a primary mixer 2 and a second intermediate frequency through a secondary mixer 5, the frequency received from the antenna is frequency error at the secondary intermediate frequency. Voltage controlled temperature compensation reference oscillator 21 for inputting a DC voltage corresponding to the reference clock divider 51 for dividing the output from the oscillator 21, voltage controlled oscillator 17, the voltage controlled oscillator ( A prescaler 11 connected to the prescaler 11, a programmable counter 12 connected to the prescaler 11, a phase comparator 13 connected to the programmable counter 12 and the reference clock divider 15, and the phase comparator 13. Characterized in that it is configured to apply the output of the primary PLL circuit 20 composed of a low pass filter 14 to the output of the voltage controlled oscillator 17 by filtering the output of Synthesizer. The DC voltage input to the voltage controlled temperature compensation reference oscillator 21 is generated from the secondary PLL circuit 30 that receives the secondary intermediate frequency from the secondary mixer 5. Featuring a frequency synthesizer. 3. The secondary PLL circuit (30) of claim 2, wherein the secondary PLL circuit (30) comprises: a programmable counter (31) for receiving the secondary frequency, a reference oscillator (35), a reference clock divider (34) connected to the reference oscillator (35), A phase comparator (33) connected to said reference clock divider (34) and a programmable counter (31), and a low pass filter (32) connected to said phase comparator (33).

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