KR920003519A - Stacked Cell Manufacturing Method and Structure - Google Patents

Stacked Cell Manufacturing Method and Structure Download PDF

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Publication number
KR920003519A
KR920003519A KR1019900010604A KR900010604A KR920003519A KR 920003519 A KR920003519 A KR 920003519A KR 1019900010604 A KR1019900010604 A KR 1019900010604A KR 900010604 A KR900010604 A KR 900010604A KR 920003519 A KR920003519 A KR 920003519A
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KR
South Korea
Prior art keywords
stacked cell
polysilicon
source drain
drain junction
cell manufacturing
Prior art date
Application number
KR1019900010604A
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Korean (ko)
Other versions
KR930011544B1 (en
Inventor
강대관
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900010604A priority Critical patent/KR930011544B1/en
Publication of KR920003519A publication Critical patent/KR920003519A/en
Application granted granted Critical
Publication of KR930011544B1 publication Critical patent/KR930011544B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

적층형 셀 제조 방법 및 구조Stacked Cell Manufacturing Method and Structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도(A)∼(G)는 본 발명에 따른 적층형 셀 제조 공정도.2 (A) to (G) show a stacked cell manufacturing process according to the present invention.

Claims (2)

다결정 폴리실리콘 사이드월 스페이서를 이용하여 트랜지스터의 n+소오스 드레인접합을 형성함과 동시에 다결정 폴리실리콘 사이드월 스페이서를 노드용 폴리실리콘과 접촉시켜 캐패시터노드 전극으로 사용하도록 하는 것을 특징으로하는 적층형셀제조방법.A method of manufacturing a stacked cell comprising: forming an n + source drain junction of a transistor using a polycrystalline polysilicon sidewall spacer and contacting the polycrystalline polysilicon sidewall spacer with polysilicon for a node to use it as a capacitor node electrode. n+소오스 드레인 접합 면적을 줄이고 n+소오스 드레인 접합이 격리산화막이 닿지않게 하며 노우드용 폴리실리콘과 접속되어 캐피시터 전극으로 사용되는 다결정 폴리실리콘과 접속되어 캐패시터 전극으로 사용되는 다결정 폴리실리콘사이드월 스페이서를 포함하여 구성된 것을 특징으로 하는 적층형 셀 구조.Includes polycrystalline polysilicon sidewall spacers to reduce n + source drain junction area, prevent n + source drain junction from contacting isolation oxide, and connect polycrystalline polysilicon used as capacitor electrode by connecting with polysilicon for Norwood Stacked cell structure, characterized in that configured to. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010604A 1990-07-13 1990-07-13 Method of fabricating for stacked cell KR930011544B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900010604A KR930011544B1 (en) 1990-07-13 1990-07-13 Method of fabricating for stacked cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900010604A KR930011544B1 (en) 1990-07-13 1990-07-13 Method of fabricating for stacked cell

Publications (2)

Publication Number Publication Date
KR920003519A true KR920003519A (en) 1992-02-29
KR930011544B1 KR930011544B1 (en) 1993-12-10

Family

ID=19301203

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010604A KR930011544B1 (en) 1990-07-13 1990-07-13 Method of fabricating for stacked cell

Country Status (1)

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KR (1) KR930011544B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329748B1 (en) * 1995-05-22 2002-08-27 주식회사 하이닉스반도체 Mosfet having ldd structure for preventing drain junction leakage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100329748B1 (en) * 1995-05-22 2002-08-27 주식회사 하이닉스반도체 Mosfet having ldd structure for preventing drain junction leakage

Also Published As

Publication number Publication date
KR930011544B1 (en) 1993-12-10

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