KR920002599B1 - Monitor detection circuit - Google Patents

Abstract

The circuit checks the fourth and the seventh pin of a monitor four times and discriminates the types of a monitor. The circuit includes a monitor detector for transmitting monitor detection signals through pins (P4,PB4,P1,PB1) according to gate enable signals and output buffer enable signals, a detection signal transmitter for transmitting the switebing signal obtained by decoding the detection signals, and a controller for generating output buffer enable signal and gate enable signals.

Description

Automatic monitor detection circuit

1 is a conventional monitor detection circuit diagram.

2 is a monitor detection circuit diagram of the present invention.

3 is a discrimination circuit diagram of the present invention.

4 is an FDC collection circuit diagram according to the present invention.

5 is a waveform diagram of FIG. 3 in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

2, 4, 15-18: D flip-flop 7-10: counter

21: Decoder B1-B3, B5-B7: Three-state buffer

B4, B8: Buffer P4, PB4, P7, PB7: Pin Name

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to all computer systems, and more particularly to circuitry for determining the type of monitor attached to a computer.

A typical computer requires the user to use a monitor suitable for the set-up state of the system or a video board suitable for the type of monitor. The video technology is mono mode, CGA (color). The development and expansion of the Graphic Adapter mode and the Enhanced Graphic Adapter mode (EGA) make it difficult to match the video mode and the monitor. In the conventional monitor detection circuit, as shown in FIG. 1, the state of MT0.MT1 at power-on is read to determine the monitor type as shown in Table 1 below.

TABLE 1

In the case of the mono monitor, since pin 4 = no connection (hereinafter referred to as N.C), MTO = low, and pin 7 = video signal, so MT1 = high.

In the case of a color monitor, pin 4 = green signal, so MTO = high, and pin 7 = N.G, so MT1 = low.

In the case of the EGA monitor, MTO = high because pin 4 = green signal and MT1 = high because pin 7 = blue signal.

There is a problem in that the monitor cannot be properly detected due to noise on the logic to determine the monitor type in the above manner.

Accordingly, an object of the present invention is to check the state of pin 4 and pin 7 of an external CRT device (monitor) four times and store the result in the main memory each time, and after reading the value later, any type of monitor It is to provide an automatic monitor detection circuit that can determine whether the connection.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a monitor detection circuit diagram of the present invention, and P4 is controlled by controlling the first and second gate enable signals ENL1 and ENL2 and the output buffer enable signal OBENL according to the state connected to pins 4 and 7 of the monitor. And monitor detection means comprising three-state buffers B1-B3, B5-B7, buffers B4, B8, and resistors R1-R6 for outputting the monitor detection signals to pins PB4, P7, and PB7.

3 is a discrimination circuit diagram of the present invention, in which a monitor detection signal applied from P4 and PB4, P7, and PB7 pins of the monitor detection means is input, decoded according to the state of mux A and mux B applied from the outside, and the switch signal SWTS. Discriminant output means consisting of a D flip-flop 15-18 and an oragate 19 and 20 and a decoder 21 and an inverter 22 for outputting the " The counters 7-10 and the end gates 11 and 12 and the inverters 13 and 14 to control the output of the discrimination output means and the second gate enable signal ENL2 by the ease signals P1 and P2. The discrimination output control means and the control signal FCO applied from the outside by the clock signal CLOCK are latched to control the first gate enable signal ENL2 and the output buffer enable signal OBENL. Copper consisting of flops (2, 4) and end gates (3) and inverters (5, 6) Constitute the control means.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. 2-5.

The basic method of detecting various types of displays is as shown in <Table 2>, and the connections between pin 4 and pin 7 of the D-sub9 video port are different for each display.

TABLE 2

2 shows a monitor detection circuit, and the truth table detected according to each monitor type is shown in the following <Table 3> and described below.

TABLE 3

When pins 4 and 7 are connected to the monitor, the signals coming into these pins are output through the tri-state buffers B1 and B5, respectively, under the control of the output buffer enable signal OBENL, and applied to the PB4 and PB7 pins. Applied to P48. Pins 4 and 7 are connected to the monitor and enable first and second gates such as the 5d and 5d wave forms, which are the control signals of the tri-state buffers B2-B3 and the tri-state buffers B6-B7. The signals ENL1 and ENL2 are for opening and closing the gates for monitor detection, and as the control signals of the tri-state buffers B1 and B5, an output buffer enable signal OBENL such as the waveform of FIG. 5e is applied.

P40, P41, P42, P48, P49, P51, P55, and P56 are pin terminals for auto-detection of 68-pin monitors. Resistors (R1-R6) are resistors that are level-adjusted to produce the correct monitor detection signal with pins P4, PB4, P7, and PB7.

FIG. 3 is a circuit for determining the result of detection in FIG. 2, and FIG. 4 is a collection circuit of the FDC and the operation thereof will be described below.

First, as shown in FIG. 5A, the control signal FCO as shown in FIG. 5 is activated. As a result, the signal output to pins P4, PB4, P7, and PB7 is input to the D flip-flop 15-18 input terminal D. .

In other words, the D flip-flop 15 output signal is logically summed through the orifice 19 and the D flip-flop 17 according to the mux B and the mux A applied from a PBI (Paradise Buffer Interface). 18) The decoder 21 decodes the output signal by OR through the oragate 20 to output the switch signal SWTS.

If mux B and mux A are 11, the result is written to switch 4 (SWTS) to bit 4 of video input / output (I / O) port 3C2H, which is a line to the CRT.

The bit 4 of the video input / output (I / O) port 3C2H is read and written to the bit 3 of 488H of the main memory.

On the other hand, if the mux B and the mux A are outputted to 10, the process as described above shifts bit 3 of the main memory 488H to bit 2, and reads bit 4 of the video input / output port 3C2H to bit 3 of the 488H of the main memory. Light it.

In addition, outputting the mux B and the mux A to 01 causes the contents of the main memory 488H to be bit-shifted (bit 3 to bit 2, bit 2 to bit 1), and bit 4 of the video input / output (I / O) port 3C2H is read. Write to bit 3 of main memory 488H.

When outputting mux B and mux A to 00, the process of 11 is performed to shift the contents of main memory 488H to 1 bit (bit 3 → bit 2, bit 2 → bit 1, bit 1 → bit 1), and then input / output port 3C2H. Read bit 4 of the bit and write it to bit 3 of the main memory 488H.

The lower bit of main memory 488H is read to determine the connected monitor type as shown in Table 4 below.

Table 4

Signals input to the P4, PB4, P7, and PB7 pins are output through the D flip-flop 15-18, and are controlled by the paging signals P1 and P2. The phase signals P1 and P2 are counted by a counter 7-10 for adjusting the time until the contents of the main memory 488H are shifted by one bit according to the clock signal CLK as shown in FIG. 5B. 14) and the clock signals through the inverter 14 and the phase signals P1 and P2 such as waveforms 5f and 5g through the AND gates 11 and 12 when applied to the AND gates 11 and 12, respectively. Will control the D flip-flop 15-18. In addition, the phase signal P2 generates the second gate enable signal ENL2 through the inverter 13. In addition, the output buffer enable signal OBENL and the first gate enable signal BNL1 for controlling the gates of the single monitor detection circuit are generated by the control signal FCO. When the control signal FCO is input to the input terminal D of the AND gate 3 and the input terminal D of the D flip-flop 2, the control signal FCO is latched by the clock signal CLOCK to the other input terminal to the AND gate 3. Is entered. The signal output through the AND gate 3 controls the reset terminal R of the D flip-flop 4.

Thus, the signal applied from the counter 8 is applied to the clock terminal C of the D flip-flop 4 through the inverter 5 and latched by this signal, so that the first gate enable signal ENL1 and the inverter 6 are applied. An output buffer enable signal (OBENL) is generated through the control panel and controls the operation of the counter 7-10.

As described above, the type of monitor attached to the system can be completely determined, and it is also 100% compatible with IBM's monitor detection logic, which can be used in future video board production.

Claims (3)

In the monitor detection circuit, the monitor detection signal is transferred to the P4, PB4, P7, and PB7 pins by controlling the first and second gate enable signals and the output buffer enable signal according to the state connected to the pins 4 and 7 of the monitor. A monitor detection means for outputting and a monitor detection signal applied from P4, PB, P7, and PB7 pins of the monitor detection means, and decoded according to the state of mux A and mux B applied from the outside to output a switch signal Output means, discrimination output control means for controlling the output of the discrimination output means and the second gate enable signal by the phase signals P1 and P2 generated by counting the clock signal, and applied from the outside by a clock signal. Automatic control detection, characterized in that the control signal (FCO) is latched to the operation control means for controlling the first gate enable signal and the output buffer enable signal Circuit. The automatic monitor detection circuit according to claim 1, wherein the monitor is detected by checking pins 4 and 7 having different connections among the 9-pin monitors. 3. The auto-monitor detection circuit according to claim 2, wherein the states of pins 4 and 7 are checked four times.

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