KR920001956B1 - Floppy disk controller - Google Patents

Abstract

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Description

Floppy Disk Control Circuit

1 is a block diagram showing the configuration of a conventional floppy disk driver control system.

2 is a block diagram showing the configuration of a floppy disk driver control system according to a first embodiment of the present invention.

3 shows the operation of the system shown in FIG.

4 is a block diagram showing a configuration of a floppy disk driver control system according to a second embodiment of the present invention.

5 shows the operation of the system shown in FIG.

6 is a diagram showing the configuration of a floppy disk driver control system according to a third embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

31: CPU 32: FDC

33: FDD 134: motor driver

135: motor status detector 136: index detector

137: read circuit 138: write circuit

139: micro switch

The present invention relates to a floppy disk control circuit for controlling a floppy disk device, and more particularly, to a peripheral circuit improvement of a floppy disk controller for controlling a floppy disk device by receiving an index signal and a read data signal.

Floppy disk devices (FDD) are widely used as external (auxiliary) storage devices of computer systems. FDD is controlled by a floppy disk controller (FDC). As a commercially available FDC, the FDC of the µPD765 series by the Japan Electric Co., Ltd. is known, for example. A schematic configuration of an FDD control system using the FDC of this µPD765 series is shown in FIG. In FIG. 1, in the actual product, a VFO or the like which is a separate chip component from the FDC is also collectively shown as the FDC 32.

The system of FIG. 1 includes a CPU 31 for outputting a control command for reading and writing data to a floppy disk; An FDC 32 for controlling FDD in accordance with a command of the CPU 31; It consists of an FDD 33 which drives a floppy disk under the control of the FDC 32.

As shown in FIG. 1, the FDC 32 controls the FDD 33 by exchanging a plurality of signals with the FDD 33, reads the data stored in the floppy disk, and writes the data to the floppy disk. Record it.

A signal exchanged between the FDC 32 and the FDD 33 will be described.

The MOTOR ON signal 311 is a signal for instructing the rotation of the spindle motor for rotating the floppy disk. The signal 312 is a signal indicating that the rotation speed of the floppy disk is constant. The STEP signal 313 is a signal instructing to move the read / write head of the data of the FDD 33 by one track. The DIR signal 314 is a signal indicating the moving direction of the head when the STEP signal 313 is given. The TRACKO signal 315 is a signal indicating whether or not the track in which the read / write head is currently located is the reference track position (home position). The INDEX signal 316 is a signal indicating a position serving as a reference for recording / reading in one track. The RDATA signal 317 is a signal representing data read from the floppy disk by the read / write head. The WDATA 318 is a signal representing data to be written to a floppy disk. The WGATE signal 319 is a signal indicating whether the current operation of the FDD 33 is a read operation or a write operation.

The FDC 32 is controlled by a command issued by the CPU 31 and outputs the various signals to control the FDD 33. The FDC 32 reads data from the floppy disk in accordance with the RDATA signal 317 and the INDEX signal 316 to notify the CPU 31 of the interrupted signal INT by returning the end of the indicated operation.

In the first configuration, a time of 500 ms or more is required after the spindle motor in response to the MOTOR ON signal 311 starts to rotate until the rotation of the motor is stabilized and data can be written / read. Do. In addition, a time of 18 ms or more is required for the head position to stabilize after the head starts moving in response to the STEP signal 303.

The time until the spindle motor starts to rotate and stabilizes, or the time after the head starts to move and stabilizes, is collectively called a state transition time.

In the conventional FDD system, the CPU outputs a motor rotation command or a head move command, and then measures the time with a software timer or the like, and then performs the following operation after the state transition time has elapsed. The reason why the CPU 31 performs this operation is that both the FDC and the FDD have no function to secure the state transition time, and the CPU 31 needs to secure the state transition time. However, if such a technique is adopted, the CPU 31 cannot perform any other work during the state transition time. In particular, when a program is executed in multiple tasks, all applications are stopped during the state transition time. To avoid this situation, the CPU had to perform complex processing or use hardware timers.

In order to solve the above drawback, the inventor of the present invention has found that the FDC controls the FDD according to the instruction from the CPU, the FDC normally outputs the INT signal to the CPU after receiving the INDEX signal and the RDATA signal, and Since the FDC uses all the write / read operations except for the format operation as the detection source of the ID selector by the RDATA signal, and the format operation uses the index signal as the source, while the operation of the moving parts such as the head and the motor is unstable, We found that gates two signals to wait for the FDC.

Thus, the floppy disk control apparatus according to the present invention receives a control command from the CPU (central processing unit) 11 and generates a MOTOR ON signal and a read / write head which instructs the rotation of the floppy disk according to the control command. Outputting a STEP signal instructing to move to the floppy disk driver 13, the READY signal indicating that the rotation speed of the floppy disk reaches a predetermined value in the floppy disk driver, an INDEX signal indicating a reference position on the track, and A floppy disk controller 12 which receives an RDATA signal including read data from a profile disk and controls reading of data from the floppy disk and writing of data to the floppy disk according to the signal; First prohibiting means connected to the floppy disk driver and the floppy disk controller and prohibiting the supply of the INDEX signal and the RDATA signal to the floppy disk controller when the READY signal is not being output; It is assumed that the interface circuit 100 includes at least one of the second prohibition means for prohibiting the supply of the INDEX signal and the RDATA signal to the floppy disk controller until the output is passed for a predetermined period.

According to the present invention, the floppy disk controller reads data from the floppy disk after the operation of the movable portion is stabilized. For this reason, it is not necessary for the CPU to measure the transition time, and the processing power of the CPU can be improved. In addition, since both the INDEX and RDATA signals are gated, the floppy disk controller does not operate or give up.

Next, an FDD control system according to the first embodiment of the present invention will be described. This first embodiment has a configuration in which the time until the rotation is stabilized after the spindle motor for rotating the floppy disk starts to rotate and the CPU can execute other tasks. In FIG. 2, VFOs and the like, which may become separate chips in actual products, are collectively shown as FDCs.

Next, the configuration of the FDD control system according to the first embodiment will be described with reference to FIG. The CPU 11 and the FDC 12 are connected by a bus 14, and the CPU 11 outputs an operation command to the FDC 12, and receives the interrupt signal INT from the FDC 12.

The FDC 12 is an FDC having a function corresponding to the µPD765 series, and can be considered to be functionally divided into a timing / command control unit, an FDD control unit, a read control unit, a write control unit, and the like.

The timing / command control unit receives a command from the CPU 11, and outputs a control signal for analyzing and executing the indicated control. The timing / instruction control unit outputs an interrupt signal to the CPU 11 when executing the instruction from the CPU 11. The recording control section outputs write data as a WDATA signal from the CPU 11 under control to the timing / command control section, outputs a WGATE signal, and instructs data recording. The read control section receives data (a pulse string in which timing pulses and data pulses are mixed) through the VFO when read by the read / write head of the FDD 13 under the control of the timing / command control section, and read data to the CPU 11. Output The FDD control section outputs a STEP signal and a DIR signal when the CPU 11 instructs the head to move under the control of the timing / command control section, and outputs a MOTOR ON signal when the CPU 11 instructs the rotation of the spindle motor.

The STEP and DIR signals from the FDC 12 are supplied to the head driver 132 which moves the position of the read / write head 131 in the FDD 13. The MOTOR ON signal from the FDC 12 is supplied to the motor driver 134 which controls the spindle motor 133 which drives the floppy disk. The motor operation state detector 135 in the FDD 13 detects the rotation state of the spindle motor, and outputs a READY signal when the rotation state of the motor is stabilized. The index detector 136 of the FDC 13 detects an index (index hole or the like) provided in the floppy disk, and outputs an INDEX signal when detected.

The read circuit 137 of the FDD 13 amplifies the analog signal read by the read / write head 131, converts it into a pulse signal, and outputs it as an RDATA signal.

The recording circuit 138 of the FDD 13 receives the WDATA signal and the WGATE signal from the FDC 12, supplies the write data to the read / write head 131, and writes the data to the floppy disk. The microswitch 139 of the FDD 13 turns on when the head 131 is in the home position and outputs the signal TRACKO.

An interface circuit 100 is provided between the FDC 12 and the FDD 13. This interface circuit 100 is composed of end gates 111 and 112. The READY signal is commonly supplied to one of the input terminals of the AND gates 111 and 112. The INDEX signal is supplied to the other input terminal of the AND gate 111. The RDATA signal is supplied to the other input terminal of the AND gate 112. The output signal of the AND gate 111 is supplied to the index signal input terminal of the FDC 12, and the output signal of the AND gate 112 is supplied to the RDATA signal input terminal of the FDC 12.

The signals shown in FIG. 2 are basically the same as the signals used conventionally, but will be described in detail with respect to the signals having important functions in this embodiment.

(1) READY

The READY signal indicates whether or not the rotation speed of the floppy disk is stable. When the floppy disk is inserted into the FDD 13 and the floppy disk starts to rotate and the rotation speed becomes constant, the READY signal is brought to the logical # 1 level. The READY signal at the logical '1' level indicates that data can be written / read by the floppy disk.

(2) STEP

STEP signal is used to move the head. The head driver 132 moves the read / write head 131 of the FDD 13 one track at the trailing edge of the pulse included in the STEP signal (transition point from logic # 1 'to # 0'). However, if the read / write head 131 is writing data to the floppy disk, the head driver 132 does not move the read / write head 131. The position of the read / write head 131 is stabilized after 18 ms at the trailing edge of the last pulse included in the STEP signal. After the position of the read / write head 131 is stabilized, the data can be written to the floppy disk and the data can be read to the floppy disk.

(3) MOTOR ON

The MOTOR ON signal is used to move the spindle motor. At the logic # 1 level, the spindle motor rotates and stops at the logic # 0 level. The start up time of the spindle motor is about 500 ms. When the floppy disk is not inserted into the FDD 13, the motor driver 134 does not rotate the spindle motor even if the MOTOR ON signal is at the logic # 1 level.

(4) INDEX

The INDEX signal is a signal indicating the start of a track. The INDEX signal is a pulse at the logic # 1 level level once per desk rotation. When no floppy disk is loaded in the FDD 13, this signal is at the logic level 0 level.

(5) RDATA

The RDATA signal is obtained by converting an analog signal read from a floppy disk into a pulse signal, and is composed of a pulse train in which data pulses of clock pulses are mixed. The leading edge of each pulse represents the read data.

Next, the operation of the system having the configuration shown in FIG. 2 will be described with reference to FIG. FIG. 3 shows the operations of the CPU 11, FDC 12, FDD 13, and interface circuit 100 in FIG. 2 in time series.

In this embodiment, it is assumed that the time until the rotation of the spindle motor is stabilized is secured on the FDC side, and it is assumed that the CPU 11 wants to read data from the floppy disk which is currently stopped. The CPU 11 outputs a motor operation command to the FDC 12 via the bus 14 (step S1). In response to a command from the CPU 11, the floppy disk controller 12 outputs a MOTOR ON signal (it is set at # 1 level) (step S2). In response to the MOTOR ON signal, the motor driver 134 rotates the spindle motor 133 (step S3).

After outputting the motor operation command, the CPU 11 outputs the next command, for example, a data read command (step S4) without waiting for the elapse of the state transition time (step S4), and shifts to another process (step S5).

In accordance with the read command output in step S4, the FDC 12 attempts to read data from the floppy disk. However, at the beginning of the rotation of the motor 132, the rotation of the motor 132 is unstable, and the READY signal is at the '0' level. For this reason, the AND gates 111 and 112 are closed, and the INDEX signal and the RDATA signal are not supplied to the FDC 12. For this reason, the FDC 12 enters the standby state (step S6) and waits for the INDEX signal and the RDATA signal to be supplied.

When the state transition time has elapsed and the rotation of the floppy disk is stabilized (step S7), the motor state detector 135 outputs a READY signal (step S8). In response to the READY signal, the AND gates 111, 112 ) Is opened, and the INDEX signal and the RDATA signal are supplied to the FDC 12 (step S8). The FDC 12 executes a data read operation based on the RDATA signal and the INDEX signal, and outputs an interrupt signal INT (step S9). The CPU 11 stops the currently executing process in response to the interrupt signal INT. The CPU 11 receives the data read by the floppy disk controller 12 in the interrupt processing routine (step S10), and moves to the next process.

Next, a case will be considered in which the CPU 11 instructs recording of data in step S4. The FDC 12 performs a read operation once to find a sector whose purpose is to write data. For this reason, the operation | movement of the said step S4-step S9 is performed as it is. The CPU supplies the write data to the FDC 12 at the point of time when the ID data detects that the head has reached the desired sector in the interrupt processing of step S10. The FDC 12 outputs the WDATA signal and the WGATE signal, and records predetermined data in a desired sector of the floppy disk. If the FDC 12 detects the INDEX signal more than the specified number of times before receiving the RDATA signal, it gives up. Therefore, when only the RDATA signal is gated using the READY signal, the FDC 12 receives the INDEX signal more than the prescribed number of times, and the FDC 12 is prohibited. In addition, the FDC 12 may operate incorrectly upon receiving an unstable RDATA signal. Therefore, if only the INDEX signal is gated using the READY signal, there is a possibility that the FDC 12 may operate incorrectly due to unstable RDATA. As a result, when both the INDEX signal and the RDATA signal are gated using the READY signal, the FDC 12 can wait for the state transition time without erroneous operation or prohibition.

The floppy disk controller 12 performs all write / read operations except for the format operation based on the detection of the ID selector by the RDATA signal, and the format operation is based on the INDEX signal, so that the RDATA and INDEX signals are gated. Is a necessary and sufficient condition for waiting the FDC 12 for the state transition period.

Next, a second embodiment of the present invention will be described with reference to FIG. 4 is a configuration for ensuring the transition time accompanying the movement of the read / write head on the FDC side.

The basic configuration of FIG. 4 is similar to the configuration shown in FIG. 2 and is described based on the feature points. The characteristic point is that the interface circuit 100 is replaced with the interface circuit 200. The interface circuit 200 is composed of a retrigger monostable multivibrator (retriggerable one short) 211, and end gates 212, 213. The retrigger ball monostable multivibrator 211 is triggered by the falling of the STEP signal, and outputs a pulse signal for approximately 18 ms or more. The multivibrator 211 is retriggered when the STEP signal arrives again during the output of the pulse signal. The Q-bar output of the monostable multivibrator 211 is commonly supplied to one input terminal of the AND gates 212 and 213. The other input terminal of the AND gate 212 is supplied with an INDEX signal from the floppy disk drive 13. The RDATA signal is supplied to the other input terminal of the AND gate 213. The output terminal of the AND gate 212 is connected to the RDATA signal input terminal of the floppy disk controller 12.

The STEP signal supplied to the multivibrator 211 is a signal used to move the head. At the trailing edge of the pulse included in the STEP signal (transition point from logic # 1 'to # 0'), the head driver moves the read / write head one track. However, if the FDD 13 is writing data to the floppy disk, the head driver does not move the read write head. The read / write head is stabilized after 18 ms at the edge of the last step pulse, and after the stabilization, the operation of reading and writing data to the floppy disk becomes possible.

Next, with reference to FIG. 5, the operation of the system shown in FIG. 4 will be described. 4 is a configuration in which the movement time of the head is secured on the FDC side, and it is assumed that the CPU attempts to read data after moving the position of the read / write head.

The CPU 11 outputs a head movement command (step S21). This movement command is output one or more times depending on the number of tracks the head is to move. The CPU 11 outputs the next command, for example, a data read command (step S22) without waiting for the passage of the state transition time, and moves on to the next process (step S23).

In response to the head movement command, the FDC 12 outputs a one-step STEP signal for one head movement command (step S24). Further, even if the head is moving, a plurality of STEP signals can be provided to move a plurality of tracks.

The head driver of the FDD moves the head one track in the direction specified by the DIR signal in response to one STEP signal (step S25).

The monostable multivibrator 211 is triggered by the STEP signal, and the Q bar output is brought to the '0' level (step S26). In response to the Q bar signal at the '0' level, the AND gates 212 and 213 are closed. For this reason, the INDEX signal and the RDATA signal are blocked by the AND gates 212 and 213 and are not supplied to the FDC 12. The multivibrator 211 is of a retrigger type, and is retriggered every time the STEP signal is output (step S27), and the Q bar output continues to be at the '0' level. For this reason, after the multivibrator 211 is finally retried (after the output of the last STEP signal (pulse)), the AND gates 212 and 213 continue to close until approximately 18 milliseconds have elapsed.

In response to a read command from the CPU 11, the FDC 12 attempts to read data. However, since the INDEX signal and the RDATA signal are not supplied to the FDC 12, the FDC 12 cannot read data and enters the standby state (step S28).

When 18 milliseconds have passed from the edge of the last pulse of the STEP signal, the read / write head of the FDD 13 is stabilized (step S29). After that, the Q-bar output of the monostable multivibrator 211 is set at the level of '1' (step S30). For this reason, the AND gates 212 and 213 are opened, and the INDEX signal and the RDATA signal are supplied to the FDC 12 (step S31). The FDC 12 performs the data read operation based on the INDEX signal and the RDATA signal. Then, the interrupt request is generated to the CPU 11 by the INT signal (step S32).

The CPU 11 receives the interrupt request from the FDC 12, stops the currently executing process, receives the read data from the FDC 12 in the interrupt processing routine (step S33), and proceeds to the next process.

Next, consider a case in which the CPU instructs the recording of data and outputs the recording data in step S22. The floppy disk controller 12 performs a read operation once to find a sector for which data is to be written. For this reason, the operation | movement of the said step S23-S32 is performed. Then, when the CPU 11 detects that the head reaches the desired sector in the interrupt processing of Step S33, the CPU 11 supplies the write data to the FDC 12, and the FDC 12 supplies the WDATA. Signal and WGATE signal are output, and the desired data is written to the floppy disk.

The FDC 12 is prohibited if it detects the INDEX signal more than the specified number of times before receiving the RDATA signal. Therefore, when only the RDATA signal is gated using the READY signal, the FDC 12 is prohibited by receiving the INDEX signal more than the specified number of times. In addition, the FDC 12 may operate incorrectly upon receiving an unstable RDATA signal. Therefore, if only the INDEX signal is gated with the output signal of the multivibrator 211, there is a possibility that the RDC 12 may operate incorrectly due to unstable RDATA. Therefore, when both the INDEX signal and the RDATA signal are gated using the READY signal, the FDC 12 can wait for a transition time without erroneous operation or prohibition.

The FDC 12 is based on the detection of the ID sector by the RDATA signal for all write / read operations except for the format operation, and the format operation is based on the INDEX signal. 12) Necessary conditions for waiting are made.

In the above embodiment, the state transition time of the motor and the state transition time of the head are separately considered, but the configuration shown in FIG. 6 can cope with any of them. The configuration of FIG. 6 corresponds to the combination of the configurations of FIG. 2 and FIG.

In the above embodiment, the CPU 11 executes read / write in the interrupt process in response to the interrupt signal from the FDC. However, the present invention is not limited thereto, and the read / write operation may be performed by checking the execution state of the FDC, for example, by the boring process of the CPU 11.

In the above embodiment, the FDC 12 and the interface circuits 100 and 200 are considered to be separate configurations. However, in the super-integration technique, the portions indicated by the broken lines 300 of the second, fourth and sixth degrees are shown. 1 chip may be used. If the portion 300 is made into one chip, the configuration of the floppy disk control system can be simplified and the handling can be simplified.

In the above embodiment, the state transition time of the motor is 500 ms and the state transition time of the read / write head is 18 ms, but the present invention is not limited to this, and the state transition time may be any value. However, the pulse width of the multer vibrator 311 is adjusted in accordance with the length and length of the state transition time of the read / write head.

The interface circuit used in the present invention is not limited to the interface circuit shown in the above embodiment, and any configuration may be used as long as the INDEX signal RDATA signal is not supplied to the FDC 12 during the state transition time. For example, the multivibrator 211 can be replaced with a timer.

The floppy disk controller used in the above embodiment assumes the µPD765 series, a FDC manufactured by Nippon Denki Co., Ltd., but is effective if the same control method is used in other FDCs. As FDD, any of 3, 5, 5, and 8 inches in general may be used.

According to the embodiment, the CPU can turn the time spent on the conventional state transition time to other processing. In the CPU, the time of 18 ms or 500 ms is a very long time, and the processing power per unit time of the CPU is also improved, and these times cannot be ignored. In this embodiment, by securing the state transition time on the FDD side, the CPU does not need to be aware of the state transition time, thereby facilitating software configuration and improving the processing efficiency of the CPU.

Claims (20)

Receives a control command from the CPU (central processing unit 11), and outputs a MOTOR ON signal for instructing rotation of the floppy disk and a STEP signal for moving the read / write head in accordance with the control command. And a READY signal indicating that the number of revolutions of the floppy disk has reached a predetermined value, an INDEX signal indicating a reference position on the track, and an RDATA signal including read data from the floppy disk. A floppy disk controller 12 for controlling reading from the floppy disk and writing of data to the floppy disk in accordance with the received signal, when connected to the floppy disk drive and the floppy disk controller and the READY signal is not being output. Supplying the INDEX signal and the RDATA signal to the floppy disk controller. An interface circuit having at least one of a first inhibiting means for inhibiting and supplying said INDEX signal and said RDATA signal to said floppy disk controller until a predetermined period of time has elapsed after the STEP signal is output. Floppy disk control device characterized in that it comprises (100). 2. The floppy disk controller of claim 1, wherein the profil disk controller receives the INDEX signal and the RDATA signal, reads data from the floppy disk, and outputs an interrupt request (INT) to the CPU. . The method of claim 1, wherein the first prohibiting means receives the READY signal at a first input terminal, receives the INDEX signal at a second input terminal, and supplies an output signal to an INDEX signal input terminal of the floppy disk controller. A first end circuit; And a second end circuit configured to receive the READY signal at a first input terminal, receive the RDATA signal at a second input terminal, and supply an output signal to an RDATA signal input terminal of the floppy disk controller. Floppy Disk Control Unit. 2. The apparatus of claim 1, wherein the second prohibiting means comprises: a retriggerable pulse signal generation circuit for outputting a pulse signal having a predetermined pulse width in response to the STEP signal; A first AND circuit receiving the pulse signal at a first input terminal, receiving the INDEX signal at a second input terminal, and supplying an output signal to an INDEX signal input terminal of the floppy disk controller; And a second end circuit configured to receive the pulse signal at a first input terminal, receive the RDATA signal at a second input terminal, and supply an output signal to an RDATA signal input terminal of the floppy disk controller. Floppy Disk Control Unit. 4. The floppy disk control apparatus according to claim 3, wherein the pulse signal generation circuit includes a restable reversible monostable multivibrator. 2. The apparatus of claim 1, wherein the interface circuit includes both of the first prohibiting means and the second prohibiting means, wherein the first prohibiting means and the second prohibiting means pulse at a predetermined pulse width in response to the STEP signal. A pulse signal generating circuit 211 for outputting a signal; Receiving the pulse signal at a first input terminal, receiving the READY signal at a second input terminal, receiving the INDEX signal at a third input terminal, and supplying an output signal to the INDEX signal input terminal of the floppy disk controller. A first end circuit 212; The first input terminal receives the predetermined pulse signal, the second input terminal receives the READY signal, the third input terminal receives the RDATA signal, and outputs an output signal to the RDATA signal input terminal of the floppy disk controller. And a second end circuit (213) for supplying. The floppy disk control apparatus according to claim 1, wherein the interface circuit and the floppy disk controller are configured in one chip. The floppy disk control apparatus according to claim 1, wherein the floppy disk control apparatus further comprises the floppy disk driver for driving the floppy disk under the control of the floppy disk controller. The apparatus of claim 8, wherein the floppy disk device outputs a write command to the floppy disk controller to write data to the floppy disk, and outputs a read command to the floppy disk controller to add the CPU to read data from the floppy disk. The CPU outputs a read command or a write command, and then shifts to another operation without counting time, and the floppy disk controller reads data and then receives read data from the floppy disk controller. Floppy disk device characterized in. Said floppy disk drive means (13) having a movable portion for driving a floppy disk; When the operation of the movable portion of the floppy disk drive means is unstable, reading of data from the floppy disk drive means is stopped, and after the operation of the movable portion of the floppy disk drive means is stabilized, the floppy disk control data is read. Floppy disk control system comprising a floppy disk controller means (100, 12). 11. The floppy disk control system according to claim 10, wherein the movable part includes a motor for rotating the floppy disk, and the floppy disk control means reads data from the floppy disk after the rotation of the motor is stabilized. . 12. The apparatus of claim 11, wherein the floppy disk drive means outputs the READY signal indicating that the rotation of the motor is stable, and the floppy disk control means reads the read data after the READY signal indicates that the rotation of the motor is stable. Floppy disk control system, characterized in that. 13. The floppy disk drive means (13) according to claim 12, wherein said floppy disk drive means (13) outputs a signal (INDEX) indicating a reference position of a track of a floppy disk and read data (RDATA) from the floppy disk. 12) receives the signal indicating the reference position and the read data from the floppy disk, and the READY signal indicates that the rotation of the motor is stable, and then the signal indicating the reference position is determined based on the read data. Floppy disk control system, characterized in that for reading the data recorded on the disk. 14. The apparatus of claim 13, wherein the floppy disk control means reads out the data and then outputs an interrupt signal, and the floppy disk control means includes a CPU means for performing a control operation according to a program, wherein the CPU means includes a read command or And outputting a read data in response to the interrupt signal after executing a write command output. 11. The floppy disk control according to claim 10, wherein the movable portion includes a read / write head, and the floppy disk control means reads data from the floppy disk after the position of the read / write head is stabilized. system. The method of claim 15, wherein the floppy disk control means outputs a pulse signal (STEP) indicating the movement of the read / write head, and the floppy disk control means at the output of the last pulse of the pulse signal continuously output. A floppy disk control system, characterized in that the read data is read after a certain period of time. 17. The apparatus of claim 16, wherein the floppy disk drive means is a signal indicating a reference position of a track of the floppy disk, a signal indicating a reference position of a track of the floppy disk, and the floppy disk control means is a signal indicating a reference position of the crack. And reading the data stored in the floppy disk on the basis of the signal indicating the reference position and the read data after the predetermined period has elapsed. 18. The apparatus of claim 17, wherein the profil disk control means outputs an interrupt signal after reading the data, and the floppy disk control means includes a CPU means for performing a control operation according to a program, wherein the CPU means reads the data. And outputting a data in response to the interrupt signal after executing a command or a write command. CPU means for outputting a read command instructing reading of data to a floppy disk and moving to the next operation without measuring the time; Floppy disk drive means for driving a floppy disk; Connected to the CPU means and the floppy drive means to instruct operation movement of the movable portion of the floppy disk drive means in response to a command from the CPU means, and to store data stored in the floppy disk after the operation of the movable portion is stabilized. And a floppy disk control means for reading out the data processing system. 20. The apparatus according to claim 19, wherein the CPU means outputs a write command, and the floppy disk control means reads the stored data of the floppy disk after the operation of the movable portion is stabilized in accordance with the write command, and based on the read data. Detecting the target sector and recording the data in the desired storage area.

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