KR920001035B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR920001035B1
KR920001035B1 KR1019880012049A KR880012049A KR920001035B1 KR 920001035 B1 KR920001035 B1 KR 920001035B1 KR 1019880012049 A KR1019880012049 A KR 1019880012049A KR 880012049 A KR880012049 A KR 880012049A KR 920001035 B1 KR920001035 B1 KR 920001035B1
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polycrystalline silicon
forming
substrate
semiconductor device
window
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KR1019880012049A
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KR900005563A (en
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정순문
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The manufacturing process for a semiconductor device comprises (1) forming a contact window on the semiconductor region of the second conduction type opposite to the first conduction type formed on the surface of semiconductor device, (2) coating doped polycrystalline silicon layer on the substrate to cover the contact window region, (3) patterning the above polycrystalline silicon 1000-3000 angstrom thick using photoresist patterning, (4) coating insulation film on the whole upper surface of the substrate, (5) forming a window to expose the patterned silicon, (6) forming a window to expose the patterned silicon, (6) filling the window region with conductive material, and (7) forming electrode pattern by coating metal on the conductive material and insulation film.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1a-g도는 본 발명에 따른 일실시예의 제조공정도.1a-g is a manufacturing process diagram of one embodiment according to the present invention.

본 발명은 반도체 장치의 제조방법에 관한 것으로 특히 콘택(Contact)영역의 접촉저항을 감소시키고 단자를 개선시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of reducing contact resistance and improving terminals of a contact region.

일반적으로 반도체 장치에서 콘택부분은 단차가 심하고 접촉저항이 증가하는 경향이 있었으며 반도체 장치가 고집적화 될수록 상기 문제는 더욱 심각하였다. 상기 문제점을 동시에 해결하기 위하여 종래에는 1987년 6월 발행된 VLSI Multilevel Interconnection Conference 200-205면에 개시된 바와 같은 선택적인 CVD 텅스텐 도포방법을 이용하여 콘택영역 상부의 콘택 홀(Contact Hole)을 채우고 그위에 금속 배선층을 형성하였다.In general, the contact portion of the semiconductor device tends to have a high level of step and an increase in contact resistance, and as the semiconductor device becomes more integrated, the problem becomes more serious. In order to solve the problem at the same time, the contact hole on the upper portion of the contact region is filled using a selective CVD tungsten coating method as disclosed in the VLSI Multilevel Interconnection Conference 200-205 issued in June 1987. A metal wiring layer was formed.

상기 방법을 이용하는 통상적인 콘택 홀을 채우는 기술은 서브미크론(Submicron)반도체 장치에서 콘택홀을 채워줄 수 있고 콘택 저항도 낮출 수 있으며 장벽 금속(Barrier Metal)역할을 할 수 있는 장점이 있었다. 그러나 선택적으로 CVD 텅스텐을 도포할때 사용하는 개스인 WF 6과 기판 실리콘(Si)의 반응에 의해 정션(Junction)에서의 실리콘의 손실이 발생하며, WF 6와 분위기 개스 H2의 반응 부산물인 불소(Fluorine)개스에 의해 콘택부위의 실리콘과 산화실리콘(SiO2)의 계면 아래쪽으로의 텅스텐의 침식(Encrochment)과 정션쪽으로 파고드는 이상기공(Wormhole)들이 발생된다. 이러한 현상들은 정션에서 누설전류(Leakage Current)를 증가시키고 브레이크 다운 전압(Breakdown Voltage)을 낮추어 반도체 장치의 특성을 저하시키는 문제점이 있었다.Conventional contact hole filling techniques using this method have the advantage of being able to fill contact holes, lower contact resistance, and act as barrier metals in submicron semiconductor devices. However, the loss of silicon in the junction occurs due to the reaction of the substrate silicon (Si), which is a gas used to selectively apply CVD tungsten, and the fluorine (byproduct) reaction of WF 6 and the atmosphere gas H2. Fluorine gas causes tungsten encroachment below the interface between silicon and silicon oxide (SiO2) and contact holes that dig into the junction. These phenomena have a problem of increasing the leakage current at the junction and lowering the breakdown voltage to deteriorate the characteristics of the semiconductor device.

따라서 본 발명의 목적은 콘택 부위를 채우는 콘택 하부의 정션에서의 누설전류 및 브레이크 다운 전압을 개선하는 반도체 장치의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device that improves the leakage current and breakdown voltage at the junction of the contact lower portion filling the contact portion.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a-g도는 본 발명에 따른 실시예의 제조공정 순서에 따른 수직단면도이다.Figure 1a-g is a vertical cross-sectional view according to the manufacturing process sequence of the embodiment according to the present invention.

제1a-g도는 모오스 전계효과 트랜지스터에 드레인 및 소오스전극을 형성하는 것을 실시예로 도시하였으나 반도체 장치의 콘택을 형성하는 어떤 부분에도 이용될 수 있음을 유의하여야 한다.Although FIGS. 1A-G illustrate the formation of a drain and a source electrode in a MOS field effect transistor, it should be noted that it may be used in any portion forming a contact of a semiconductor device.

제1a도를 참조하면 P형 반도체 기판(10)상부에 필드산화막(11)으로 둘러쌓인 액티브 영역(a)이 형성되고, 상기 액티브 영역(a)의 기판 표면상에 게이트 산화막(12)이 형성되며, 게이트 산화막(12)상에 다결정 실리콘 게이트 전극(13)이 형성되고, 게이트 산화막(12)하부의 기판 표면에 서로 이격하여 형성된 기판과 반대 도전형인 고농도 n형의 소오스 및 드레인 영역(14)(15)이 형성되어 있다. 상기와 같은 제1a도는 표준 모오스 공정에 의해서 형성된 것이며 기판 상부에는 절연층(16)이 도포되어 있다. 그 다음 상기 절연막층(16)에 포토레지스트를 코팅한 후 통상의 사진공정(Photolithography)으로 포토레지스트 패턴(19)을 형성하고 이 포토레지스트 패턴(19)을 식각 마스크로 사용하여 노출된 소오스 및 드레인영역(14)(15)상부의 절연막층(16) 및 게이트 산화막층(12)을 에칭하면 제1b도와 같이 제1접속창(Contact Window)(21)(22)이 형성된다. 그 다음 기판상의 포토레지스트 패턴(19)을 제거하고 기판상부 전면에 다결정 실리콘층(24)을 통상의 저압 CVD방법으로 두께 1000-3000A 정도로 도포한 후 상기 다결정 실리콘층(24)전면에 소오스 및 드레인영역(14)(15)과 동일 도전형인 n형 불순물 비소(As) 또는 인(P)등을 이온주입하여 제3c도와 같이 형성한다. 그 다음 상기 다결정 실리콘층(24)상에 포토레지스트를 코팅하고 통상의 사진공정으로 상기 제1접속창 영역(21)(22)에 포토레지스트 패턴(26)을 형성하며 이 패턴(26)을 식각 마스크로 하여 노출된 다결정 실리콘층(24)을 식각하여 제1d도와 같이 상기 제1접속창 영역(21)(22)에 접속 다결정 실리콘 패턴(27)(28)을 형성한 후 상부의 포토레지스트 패턴(26)을 제거한다.Referring to FIG. 1A, an active region a surrounded by the field oxide film 11 is formed on the P-type semiconductor substrate 10, and a gate oxide film 12 is formed on the substrate surface of the active region a. The polycrystalline silicon gate electrode 13 is formed on the gate oxide film 12, and the highly-concentrated n-type source and drain region 14 of the opposite conductivity type to the substrate formed spaced apart from each other on the substrate surface under the gate oxide film 12. (15) is formed. 1a as described above is formed by a standard MOS process, and an insulating layer 16 is coated on the substrate. Then, after the photoresist is coated on the insulating layer layer 16, a photoresist pattern 19 is formed by a general photolithography process, and the exposed source and drain are formed using the photoresist pattern 19 as an etching mask. When the insulating layer 16 and the gate oxide layer 12 on the regions 14 and 15 are etched, first contact windows 21 and 22 are formed as shown in FIG. 1b. Then, the photoresist pattern 19 on the substrate was removed, and the polycrystalline silicon layer 24 was applied to the entire upper surface of the substrate by a conventional low pressure CVD method with a thickness of about 1000-3000A, and then the source and the drain on the entire surface of the polycrystalline silicon layer 24 were removed. An n-type impurity arsenic (As), phosphorus (P), or the like, which is of the same conductivity type as those of the regions 14 and 15, is ion implanted to form the same as in FIG. 3C. Then, a photoresist is coated on the polycrystalline silicon layer 24, and a photoresist pattern 26 is formed in the first access window areas 21 and 22 by a general photographic process, and the pattern 26 is etched. The exposed polycrystalline silicon layer 24 using the mask is etched to form the connection polycrystalline silicon patterns 27 and 28 in the first connection window areas 21 and 22 as shown in FIG. 1d, and then the upper photoresist pattern. Remove (26).

여기서 상기 다결정 실리콘(24)에 대한 패터닝 공정에 사용되는 마스크는 다결정 실리콘을 사용하는 집적회로상에서 공용으로 사용될 수 있음을 알아두기 바란다. 그 다음 접속 다결정 실리콘 패턴(27)(28)이 형성된 기판상에 두꺼운 절연막층(31)을 도포하고 단차를 개선하기 위하여 통상적인 리플로우공정(Reflow Process)등을 이용하여 평탄화를 시켜준 후 통상의 사진식각 공정(Photolithographic Process)으로 상기 접속 다결정 실리콘 패턴(28)(29)상에 제2접속창(33)(34)을 제1e도와 같이 형성한다. 그 다음 제2접속창(33)(34)이 형성된 기판상에 접속 다결정 실리콘 패턴(28)(27)상의 제2접속창 영역(33)(34)에서만 텅스텐이 도포되도록 1987년 6월 발행된 VLSI Multilevel Interconnection Conference 200-205면에 개시된 바와 같은 통상적인 선택된 CVD 텅스텐 도포방법으로 텅스텐 접속영역(36)(37)을 제1f도와 같이 형성한다. 제2접속창 영역(33)(34)에만 텅스텐이 선택적으로 도포되므로 기판은 접속창 영역을 포함하여 전체적으로 평탄하게 된다. 그 다음 상기 평탄하게 된 기판면에 제1g도와 같이 금속층(39)을 도포한 후 패턴닝을 하면 모오스 전계효과 트랜지스터가 형성된다.Note that the mask used in the patterning process for the polycrystalline silicon 24 may be commonly used on integrated circuits using polycrystalline silicon. After that, a thick insulating film layer 31 is applied on the substrate on which the connection polycrystalline silicon patterns 27 and 28 are formed and planarized by using a conventional reflow process to improve the level difference. In the photolithographic process, the second connection windows 33 and 34 are formed on the connection polycrystalline silicon patterns 28 and 29 as shown in FIG. Then issued in June 1987 so that tungsten was applied only on the second connection window regions 33 and 34 on the connection polycrystalline silicon patterns 28 and 27 on the substrate on which the second connection windows 33 and 34 were formed. Tungsten connection regions 36 and 37 are formed as shown in FIG. 1f by a conventional selected CVD tungsten application method as disclosed on pages 200-205 of the VLSI Multilevel Interconnection Conference. Since tungsten is selectively applied only to the second access window regions 33 and 34, the substrate is flat throughout, including the access window region. Next, the metal field 39 is coated on the planarized substrate surface, and then patterned to form a MOS field effect transistor.

상술한 바와 같이 본 발명은 콘택에서 다결정 실리콘 위에 텅스텐을 CVD방법으로 선택적으로 형성시키는 이층 구조방법이기 때문에 통상적인 선택적인 텅스텐의 도포방법에 의한 것보다 실리콘 산화막과 실리콘계면의 텅스텐에 의한 침식과 정션의 실리콘의 손실이 없으며 이상기공도 없어진다.As described above, the present invention is a two-layer structure method in which tungsten is selectively formed on polycrystalline silicon in a contact by CVD method. There is no loss of silicon and no abnormal pores.

따라서 본 발명은 얕은 정션(Shallow Junction)에서 통상적인 방법보다 누설전류가 감소하게 되고, 기판의 정션 실리콘의 손실이 없으므로 정션 브레이크 다운 전압도 증가한다. 또한 본 발명은 콘택부위를 이층구조로 함으로써 콘택을 채우기가 용이하고 콘택을 만들때 마스크간의 정렬 오차(Misalign)에 의한 영향을 줄일 수 있다. 또한 본 발명은 이층 이상의 다결정 실리콘을 사용하는 대규모 집적회로에 사용하므로 추가되는 마스크 공정이 없어도 되며, 다결정 실리콘층을 국부적인 내부접속(Local Interconnect)등 다른 용도로도 쓸수있는 이점이 있다.Therefore, the present invention reduces the leakage current than the conventional method at the shallow junction, and also increases the junction breakdown voltage since there is no loss of the junction silicon of the substrate. In addition, according to the present invention, since the contact portion has a two-layer structure, it is easy to fill the contact, and the influence of misalignment between masks can be reduced when making the contact. In addition, since the present invention is used in a large scale integrated circuit using two or more layers of polycrystalline silicon, there is no need for an additional mask process, and the polycrystalline silicon layer may be used for other purposes such as local interconnect.

Claims (3)

다결정 실리콘을 사용하는 집적회로에서, 제1도전형의 반도체 기판표면에 형성된 상기 제1도전형과 반대도전형인 제2도전형의 반도체 영역상에 전극을 형성하는 공정이 하기 공정을 구비하여 하기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법. (a) 제1도전형의 반도체 기판 표면에 형성된 제1도전형과 반대도전형인 제2도전형의 반도체영역 상부에 상기 반도체 영역을 소정부분 노출시키는 접속창을 형성하는 공정. (b) 상기 기판에 상기 접속창 영역을 덮을 수 있도록 도핑된 다결정 실리콘층을 도포하고 상기 집적회로내의 다른 다결정 실리콘 패터닝에도 사용되는 포토레지스트 패턴을 이용하여 상기 다결정 실리콘을 패터닝하는 공정. (c) 상기 기판상부 전면에 절연막을 도포하고 상기 다결정 실리콘 패턴 부분을 노출시키는 창을 형성하는 공정. (d) 상기 노출된 다결정 실리콘 부분 상부의 창영역을 도전성 물질로 채우는 공정. (e) 상기 도전성 물질과 절연막상에 금속을 도포하고 전극 패턴을 형성하는 공정.In an integrated circuit using polycrystalline silicon, a process of forming an electrode on a semiconductor region of a second conductive type opposite to the first conductive type formed on the surface of the semiconductor substrate of the first conductive type includes the following steps. A method for manufacturing a semiconductor device, characterized by a continuous process. (a) forming a connection window exposing a predetermined portion of the semiconductor region over the semiconductor region of the second conductive type opposite to the first conductive type formed on the surface of the semiconductor substrate of the first conductive type. (b) applying the doped polycrystalline silicon layer to the substrate so as to cover the connection window region and patterning the polycrystalline silicon using a photoresist pattern used for other polycrystalline silicon patterning in the integrated circuit. (c) forming a window for applying an insulating film over the entire upper surface of the substrate and exposing the polycrystalline silicon pattern portion. (d) filling the window region over the exposed polycrystalline silicon portion with a conductive material. (e) applying a metal on the conductive material and the insulating film and forming an electrode pattern. 제1항에 있어서, 상기 다결정 실리콘 패턴의 두께가 1000-3000A으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the polycrystalline silicon pattern has a thickness of 1000-3000A. 제1항에 있어서, 제(d)공정이 다결정 실리콘 위에 텅스텐을 선택적으로 도포하는 공정임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein step (d) is a step of selectively applying tungsten on the polycrystalline silicon.
KR1019880012049A 1988-09-16 1988-09-16 Manufacturing method of semiconductor device KR920001035B1 (en)

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