KR900005870B1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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KR900005870B1
KR900005870B1 KR1019870012923A KR870012923A KR900005870B1 KR 900005870 B1 KR900005870 B1 KR 900005870B1 KR 1019870012923 A KR1019870012923 A KR 1019870012923A KR 870012923 A KR870012923 A KR 870012923A KR 900005870 B1 KR900005870 B1 KR 900005870B1
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polycrystalline silicon
layer
semiconductor
silicide
region
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KR1019870012923A
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KR890008963A (en
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조북룡
도명근
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

a first conductive type of semiconductor substrate (1); a second conductive type of semiconductor region (2) formed onto the substrate; a polysilicon layer (6) formed on the region (2) and separated from the insulating film (2); a silicide film (7) formed onto the polysilicon layer; a buried polysilicon layer (9) formed on the silicide film; and an aluminum metal layer (10) formed onto the silicide film and polysilicon buried layer. The buried polysilicon layer is separated from the silicide film by the oxide film (8).

Description

반도체 장치의 접속구조Connection structure of semiconductor device

제1a -d도는 본 발명에 따른 제조공정도1a-d is a manufacturing process diagram according to the present invention

본 발명은 반도체 장치의 접속구조에 관한 것으로 특히 접속영역의 스텝 커버리지(Step-coverage)와 접속라인의 특성을 개선한 반도체 장치의 접속구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure of a semiconductor device, and more particularly to a connection structure of a semiconductor device with improved step coverage and connection line characteristics of a connection area.

종래 반도체 장치에서 콘택(Contact)이 필요한 부분에서는 실리콘 기판에 N+ 또는 P+의 고농도 도핑층을 형성하고 고농도 도핑층 상부에 알루미늄 또는 알루미늄과 실리콘의 합금으로 이루어지는 금속도전층의 접속라인을 형성하여 이 접속라인과 고농도 도핑된 실리콘기판 영역을 오믹콘택(Ohmic Contact)시켰다.Where a contact is required in a conventional semiconductor device, a highly doped layer of N + or P + is formed on a silicon substrate, and a connection line of a metal conductive layer made of aluminum or an alloy of aluminum and silicon is formed on the highly doped layer. The line and the heavily doped silicon substrate region were ohmic contacted.

그러나 상기 접속영역에서와 같이 실리콘과 알루미늄이 접하는 영역 특히 콘택이 1㎛2이하일 경우에는 실리콘의 석출로 인하여 오믹접속이 이루어지지 않으므로 콘택의 전기적인 오믹특성 및 콘택저항이 열화되는 문제점이 있었다. 또한 기판과 접촉하는 접속영역의 스텝커버리지(Step-coverage)가 양호하지 못한 문제점이 있었다. 상기와 같은 문제점은 점차적으로 반도체 장치가 고집적화 되어가는데 저해 요인이 되므로 서브미크론(Sub-micron) 단위의 VLSI급 소자의 제조공정에서는 더 이상 사용하기 어렵다.However, in the case where the contact between silicon and aluminum, in particular, the contact is less than 1㎛ 2 as in the connection region, ohmic connection is not made due to precipitation of silicon, there is a problem in that electrical ohmic characteristics and contact resistance of the contact deteriorate. In addition, there is a problem that the step-coverage of the connection area in contact with the substrate is not good. Such a problem becomes a detrimental factor to gradually increasing the integration of semiconductor devices, so it is difficult to use it anymore in the manufacturing process of VLSI-class devices in sub-micron units.

따라서 본 발명의 목적은 반도체 장치에서 접속영역의 전기적 특성과 스텝커버리지를 향상시킬 수 있는 반도체 장치의 접속구조를 제공함에 있다. 상기와 같은 본 발명의 목적을 달성하기 위하여 본 발명은 제1도전형의 반도체 기판과, 상기 반도체 기판 표면의 소정 영역에 형성된 상기 제1도전형과 반대도전형의 반도체 영역과, 상기 제2도전형의 반도체 영역상에 상기 반도체 영역과 접하여 형성되고 상기 제2도전형의 반도체 영역이외의 반도체 기판상에 절연막으로 이격되어 형성된 다결정 실리콘층과, 상기 다결정 실리콘층 상부에 형성된 실리사이드막과, 상기 제2도전형의 반도체영역 상부의 실리사이드 막상에 형성된 다결정 실리콘 매몰층과, 상기 실리사이드막과 다결정 실리콘 매몰층상에 형성된 알루미늄 금속층을 구비함을 특징으로 한다.Accordingly, an object of the present invention is to provide a connection structure of a semiconductor device capable of improving electrical characteristics and step coverage of a connection area in a semiconductor device. In order to achieve the object of the present invention as described above, the present invention provides a semiconductor substrate of the first conductive type, a semiconductor region of the opposite conductivity type to the first conductive type formed on a predetermined region of the semiconductor substrate surface, and the second conductive type. A polycrystalline silicon layer formed on the semiconductor region in contact with the semiconductor region and spaced apart by an insulating film on a semiconductor substrate other than the second conductive semiconductor region, and a silicide film formed on the polycrystalline silicon layer; And a polycrystalline silicon buried layer formed on the silicide film above the two-conducting semiconductor region, and an aluminum metal layer formed on the silicide film and the polycrystalline silicon buried layer.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a-d도는 본 발명에 따른 실시예의 제조공정도이다. 먼저 제1a도와 같이 P형 반도체 기판상에 소자 형성영역(Active 영역)의 패턴을 형성한 후 필드산화막(2)을 형성하여 소자 형성영역을 소자분리(Isolation)시키고 기판과 접속될 소정영역에 기판과 반대도전형인 N+가 이온주입된 반도체영역(3)을 형성한다. 또한 상기 기판상에 형성될 N웰상의 소정 접속영역에는 웰과 반대도전형인 P+의 이온주입 영역이 형성됨을 유의하여야 한다. 그다음 기판 상부 전면에 통상의 CVD 방법으로 CVD 산화막(4)을 도포하고 각 접속영역(Contact)을 형성하기 위해 통상의 사진식각 공정으로 접속창(5)을 형성한다. 그다음 제1b도와 같이 통상의 방법으로 CVD 산화막(4)과 접속창(5)영역상에 100-1000Å 정도의 다결성 실리콘(6)을 통상의 저압 CVD 방법으로 형성하고 상기 다결정 실리콘층(6) 전면에 상기 다결정 실리콘층의 저항 감소를 위하여 인(Phosphorous) 이온과 BF2 이온주입을 한다. 상기와 같이 다결정 실리콘 표면에 2가지 도전형의 이온주입을 동시에 하는 이온 혼합(Mixing)방법은 상기 P형 기판상의 N+이온주입영역, N웰상의 P+이온주입등과 접속되는 다결정 실리콘층에 별도의 마스킹 공정을 사용하지 않아도 되므로 씨모오스 공정에서 특히 효율적이다. 한편 상기 도핑된 다결정 실리콘 대신 얇은 두께의 다결정 실리콘을 도포하여 불순물 이온주입을 하지 않고 형성할 수도 있다. 그 다음 상기 다결정 실리콘층(6)상에 몰리브덴 실리사이드(Mo-silicide)(7)를 1000Å-5000Å정도로 통상의 CVD 방법으로 형성하고 상기 몰리브덴 실리사이드를 통상의 고온산화 공정으로 산화하여 상기 몰리브덴 실리사이드상에 SiO2 산화막(8)을 소정 두께 형성한다. 이때 상기와 같이 고온 산화공정으로 열처리된 몰리브덴 실리사이드는 저항값이 감소되게 된다.1a-d is a manufacturing process diagram of the embodiment according to the present invention. First, as shown in FIG. 1A, a pattern of an element formation region (active region) is formed on a P-type semiconductor substrate, and then a field oxide film 2 is formed to isolate an element formation region and to form a substrate in a predetermined region to be connected to the substrate. The semiconductor region 3 into which the + is ion-implanted is formed. It should be noted that an ion implantation region of P + opposite to the well is formed in a predetermined connection region on the N well to be formed on the substrate. Then, the CVD oxide film 4 is applied to the entire upper surface of the substrate by a conventional CVD method, and the connection window 5 is formed by a conventional photolithography process to form each contact region. Next, as shown in FIG. 1B, polycrystalline silicon 6 of about 100-1000 kPa is formed on the region of the CVD oxide film 4 and the connection window 5 by a conventional low pressure CVD method, and the polycrystalline silicon layer 6 Phosphorous ions and BF2 ions are implanted to reduce the resistance of the polycrystalline silicon layer on the front surface. As described above, the ion mixing method for simultaneously implanting two conductive types of ions onto the surface of the polycrystalline silicon is performed separately from the polycrystalline silicon layer connected to the N + ion implantation region on the P-type substrate and the P + ion implantation on the N well. It is particularly efficient in the SiMoose process since no masking process is required. Meanwhile, instead of the doped polycrystalline silicon, a thin thickness of polycrystalline silicon may be applied to form the impurity ion implantation. Molybdenum silicide (Mo-silicide) 7 is then formed on the polycrystalline silicon layer 6 at about 1000 kV-5000 kPa by the conventional CVD method, and the molybdenum silicide is oxidized by a conventional high temperature oxidation process to A SiO2 oxide film 8 is formed to a predetermined thickness. At this time, the molybdenum silicide heat-treated by the high temperature oxidation process as described above is reduced in the resistance value.

상기에서 다결정 실리콘층(6)상에 몰리브덴 실리사이드(Mosilicide)를 도포하고 산화한 실시예를 설명하였으나 티탄실리 사이드(Ti-silicide) 또는 텅스텐 실리사이드 (W-silicide)등의 다른 금속 실리사이드를 다결정 실리콘층상에 형성하고 산화공정을 진행하여도 상기 몰리브덴 실리사이드의 경우와 같은 결과를 나타냉은 이 분야의 통상의 지식을 가진자는 쉽게 이해할 수 있을 것이다. 그다음 상기 산화막(8)상에 3000Å-8000Å 정도의 다결정 실리콘(9)을 형성하고 POC13에 침적하여 상기 다결정실리콘(9)에 인 이온을 확신시킨후 별도의 마스크 없이 통상의 반응성 이온에칭방법(RIE)으로 상기 다결정 실리콘을 에칭(Etch- back)하면 제1c도와 같이 형성된다. 상기에서는 다결정 실리콘(9)의 저항을 감소시키기 위한 방법으로 POC13에 침적하는 방법을 사용하였으나 상기의 방법이외에 이온주입 또는 다른 방법을 사용할 수도 있다. 또한 상기 다결정 실리콘(9)은 불순물을 도핑하지 않고 사용할 수도 있다. 이 공정시 접속창 영역이 상기 도핑된 다결정 실리콘(9)으로 채워져서 기판이 평탄화되며 접속창 영역이외의 영역에는 다결정 실리콘이 에칭되어 산화막(8)이 노출된다. 그 다음 제1D도와 같이 상기 노출된 몰리브덴 실리사이드상의 산화막(8)을 제거한 후 기판전면에 알루미늄들의 금속층(10)을 형성한다. 상기 금속층(10)은 중량비 0-2%의 실리콘을 포함하는 알루미늄 합금, 중량비 0-2%의 실리콘과 중량비 0-2%의 구리를 포함하는 알루미늄합금을 사용할 수 있다. 상기와 같이 접속영역이 평탄해진 기판상에 알루미늄등의 금속층을 형성하면 접속영역 이외의 접속라인은 알루미늄/몰리브덴 실리사이드/다결정 실리콘 층으로 구성되며 이 접속라인을 패터닝(Patterning)하여 배선층을 형성한다.In the above, an embodiment in which molybdenum silicide (Mosilicide) is applied to and oxidized on the polycrystalline silicon layer 6 has been described. It can be easily understood by those of ordinary skill in the art that the same results as in the case of molybdenum silicide are obtained even after the formation and the oxidation process are performed. Then, the polycrystalline silicon 9 of about 3000 kV to 8000 kV is formed on the oxide film 8 and deposited on POC13 to convince the polysilicon 9 with phosphorus ions, and then a conventional reactive ion etching method (RIE) is performed without a mask. The polycrystalline silicon is etched back to form as shown in FIG. 1C. In the above, a method of dipping in POC13 is used as a method for reducing the resistance of the polycrystalline silicon 9, but ion implantation or another method may be used in addition to the above method. The polycrystalline silicon 9 may also be used without doping impurities. In this process, the junction window region is filled with the doped polycrystalline silicon 9 to planarize the substrate, and the polycrystalline silicon is etched in an area other than the junction window region to expose the oxide film 8. Then, as shown in FIG. 1D, the oxide layer 8 on the exposed molybdenum silicide is removed, and then a metal layer 10 of aluminum is formed on the front surface of the substrate. The metal layer 10 may be an aluminum alloy containing silicon in a weight ratio of 0-2%, an aluminum alloy containing silicon in a weight ratio of 0-2% and copper in a weight ratio of 0-2%. When a metal layer such as aluminum is formed on the substrate where the connection region is flat as described above, the connection lines other than the connection region are composed of an aluminum / molybdenum silicide / polycrystalline silicon layer, and the connection lines are patterned to form a wiring layer.

상술한 바와 같이 본 발명은 실리콘 기판과 배선층과의 접속하는 영역에 실리콘과 알루미늄이 접하지 않고 실리콘과 다결정 실리콘이 접하게 되므로 실리콘 기판 표면에서 실리콘의 석출현상은 일어나지 않게 된다.As described above, in the present invention, silicon and polycrystalline silicon are not in contact with the silicon substrate and the wiring layer, and silicon and polycrystalline silicon are not in contact with each other, so that precipitation of silicon does not occur on the surface of the silicon substrate.

또한 본 발명은 콘택영역이 다결정 실리콘으로 매몰되므로 접속라인의 스텝커버리지가 향상되는 이점이 있다.In addition, the present invention has the advantage that the step coverage of the connection line is improved because the contact region is buried in polycrystalline silicon.

Claims (5)

반도체 장치에 있어서, 제1도전형의 반도체 기판(1), 상기 반도체 기판 표면의 소정영역에 형성된 상기 제1도전형과 반대도전형의 반도체 영역(3)과, 상기 제2도전형의 반도체영역(2)상에 상기 반도체영역과 접하여 형성되고 상기 제2도전형의 반도체 영역이외의 반도체 기판상에 절연막(2)으로 이격되어 형성된 다결정 실리콘층(6)과, 상기 다결정 실리콘층 상부에 형성된 실리사이드막(7)과, 상기 제2도전형의 반도체영역 상부의 실리사이드막상에 형성된 다결정 실리콘 매몰층(9)과, 상기 실리사이드막과 다결정 실리콘 매몰층상에 형성된 알루미늄 금속층(10)을 구비함을 특징으로 하는 반도체 장치의 접속구조.1. A semiconductor device, comprising: a semiconductor substrate 1 of a first conductivity type, a semiconductor region 3 of a conductivity type opposite to that of the first conductivity type formed in a predetermined region on a surface of the semiconductor substrate, and a semiconductor region of the second conductivity type. A polycrystalline silicon layer 6 formed on (2) in contact with the semiconductor region and spaced apart by an insulating film 2 on a semiconductor substrate other than the second conductive semiconductor region, and a silicide formed on the polycrystalline silicon layer A film 7, a polycrystalline silicon buried layer 9 formed on the silicide film above the second conductive semiconductor region, and an aluminum metal layer 10 formed on the silicide film and the polycrystalline silicon buried layer. The connection structure of a semiconductor device. 제1항에 있어서, 상기 다결정 실리콘 매몰층과 실리사이드막의 소정의 산화막(8)으로 이격됨을 특징으로 하는 반도체 장치의 접속구조.The semiconductor device connection structure according to claim 1, wherein the polycrystalline silicon buried layer and the silicide film are separated by a predetermined oxide film (8). 제1항에 있어서, 상기 실리사이드막(8)막이 몰리브덴 실리사이드 또는 티탄실리 사이드 또는 텅스텐 실리사이드중 선택된 어느하나임을 특징으로 하는 반도체 장치의 접속구조.The semiconductor device connection structure according to claim 1, wherein said silicide film (8) film is one selected from molybdenum silicide, titanium silicide or tungsten silicide. 제1항에 있어서, 상기 알루미늄 금속층(10)이 중량비 0-2% 실리콘을 함유하는 알루미늄 합금 또는 중량비 0.2% 실리콘과 중량비 0-2% 구리를 함유하는 알루미늄 합금 중 선택된 어느 하나임을 특징으로 하는 반도체 장치의 접속구조.The semiconductor of claim 1, wherein the aluminum metal layer 10 is any one selected from an aluminum alloy containing 0-2% silicon by weight or an aluminum alloy containing 0.2% silicon by weight and 0-2% copper by weight. Connection structure of the device. 제1항에 있어서, 상기 다결정 실리콘층(6)과 다결정 실리콘 매몰층(9)이 소정 도전형의 불순물이 도핑된 다결정 실리콘층 임을 특징으로 하는 반도체 장치의 접속구조.2. The semiconductor device connection structure according to claim 1, wherein the polycrystalline silicon layer (6) and the polycrystalline silicon buried layer (9) are polycrystalline silicon layers doped with impurities of a predetermined conductivity type.
KR1019870012923A 1987-11-17 1987-11-17 Semiconductor device KR900005870B1 (en)

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