KR890008963A - Connection structure of semiconductor device - Google Patents

Connection structure of semiconductor device Download PDF

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Publication number
KR890008963A
KR890008963A KR870012923A KR870012923A KR890008963A KR 890008963 A KR890008963 A KR 890008963A KR 870012923 A KR870012923 A KR 870012923A KR 870012923 A KR870012923 A KR 870012923A KR 890008963 A KR890008963 A KR 890008963A
Authority
KR
South Korea
Prior art keywords
polycrystalline silicon
semiconductor device
conductivity type
silicide
connection structure
Prior art date
Application number
KR870012923A
Other languages
Korean (ko)
Other versions
KR900005870B1 (en
Inventor
조북룡
도명근
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870012923A priority Critical patent/KR900005870B1/en
Publication of KR890008963A publication Critical patent/KR890008963A/en
Application granted granted Critical
Publication of KR900005870B1 publication Critical patent/KR900005870B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

내용 없음No content

Description

반도체 장치의 접속구조Connection structure of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1(A)-(D)도는 본 발명에 따른 제조공정도.1 (A)-(D) is a manufacturing process diagram according to the present invention.

Claims (5)

반도체 장치에 있어서, 제1도 전형의 반도체 기판과, 상기 반도체 기판 표면의 소정영역에 형성된 상기 제1도 전형과 반대 도전형의 반도체 영역과, 상기 제2도 전형의 반도체영역 상에 상기 반도체영역과 접하여 형성되고, 상기 제2도 전형의 반도체 영역이외의 반도체 기판상에 절연막으로 이격되어 형성된 다결정 실리콘층과, 상기 다결정 실리콘층 상부에 형성된 실리사이드막과, 상기 제2도 전형의 반도체영역 상부의 실리사이드막상에 형성된 다결정 실리콘 매몰층과, 상기 실리사이드막과 다결정 실리콘 매몰층상에 형성된 알루미늄 금속층을 구비함을 특징으로 하는 반도체 장치의 접속구조.A semiconductor device comprising: a semiconductor substrate of a first conductivity type, a semiconductor region of a conductivity type opposite to that of the first conductivity type formed in a predetermined region on a surface of the semiconductor substrate, and the semiconductor region on the second conductivity type semiconductor region A polycrystalline silicon layer formed in contact with and spaced apart by an insulating film on a semiconductor substrate other than the second conductive semiconductor region, a silicide film formed on the polycrystalline silicon layer, and an upper portion of the second conductive semiconductor region. And a polycrystalline silicon buried layer formed on the silicide film, and an aluminum metal layer formed on the silicide film and the polycrystalline silicon buried layer. 제1항에 있어서, 상기 다결정 실리콘 매몰층과 실리사이드막의 소정의 산화막으로 이격됨을 특징으로 하는 반도체 장치의 접속구조.The semiconductor device connection structure according to claim 1, wherein the polycrystalline silicon buried layer and the silicide film are separated by a predetermined oxide film. 제1항에 있어서, 상기 실리사이드막이 몰리브덴 실리사이드 또는 티탄실리 사이드 또는 텅스텐 실리사이드중 선택된 어느 하나임을 특징으로 하는 반도체 장치의 접속구조.The semiconductor device connection structure according to claim 1, wherein said silicide film is one selected from molybdenum silicide, titanium silicide, or tungsten silicide. 제1항에 있어서, 상기 알루미늄 금속층이 중량비 0-2% 실리콘을 함유하는 알루미늄 합금 또는 중량비 0.2% 실리콘과 중량비 0-2% 구리를 함유하는 알루미늄 합금중 선택된 어느 하나임을 특징으로 하는 반도체 장치의 접속구조.The semiconductor device of claim 1, wherein the aluminum metal layer is any one selected from an aluminum alloy containing 0-2% silicon by weight or an aluminum alloy containing 0.2% silicon by weight and 0-2% copper by weight. rescue. 제1항에 있어서, 상기 다결정 실리콘층과 다결정 실리콘 매몰층이 소정 도전형의 불순물이 도핑된 다결정 실리콘층 임을 특징으로 하는 반도체 장치의 접속구조.The semiconductor device connection structure according to claim 1, wherein the polycrystalline silicon layer and the polycrystalline silicon buried layer are polycrystalline silicon layers doped with impurities of a predetermined conductivity type. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870012923A 1987-11-17 1987-11-17 Semiconductor device KR900005870B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870012923A KR900005870B1 (en) 1987-11-17 1987-11-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870012923A KR900005870B1 (en) 1987-11-17 1987-11-17 Semiconductor device

Publications (2)

Publication Number Publication Date
KR890008963A true KR890008963A (en) 1989-07-13
KR900005870B1 KR900005870B1 (en) 1990-08-13

Family

ID=19266066

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870012923A KR900005870B1 (en) 1987-11-17 1987-11-17 Semiconductor device

Country Status (1)

Country Link
KR (1) KR900005870B1 (en)

Also Published As

Publication number Publication date
KR900005870B1 (en) 1990-08-13

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