KR880014657A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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KR880014657A
KR880014657A KR1019880006507A KR880006507A KR880014657A KR 880014657 A KR880014657 A KR 880014657A KR 1019880006507 A KR1019880006507 A KR 1019880006507A KR 880006507 A KR880006507 A KR 880006507A KR 880014657 A KR880014657 A KR 880014657A
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layer
forming
semiconductor
manufacturing
semiconductor device
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KR1019880006507A
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KR910007099B1 (en
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마사가즈 가쿠무
테츠야 아사미
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아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이콤엔지니어링 가부시끼가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

내용 없음No content

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도의 a∼c는 반도체장치에 대한 종래의 제조방법을 설명하기 위한 단면도, 제2도의 a∼h는 본 발명의 제1실시예에 따른 반도체장치의 제조방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a conventional manufacturing method for a semiconductor device, and FIGS. 2A to 2H are cross-sectional views illustrating a semiconductor device manufacturing method according to a first embodiment of the present invention.

Claims (20)

반도체기판(18)에 제1도전층을 형성시켜 주는 공정과, 이 제1도전층위에 제1절연층을 형성시켜 주는 공정, 이 제1절연층에다 상기 제1도전층위로 접점구멍(23)을 뚫어주는 공정, 상기 접점구멍(23)이 뚫려진 상기 제1절연층(22) 위에 반도체층을 형성시켜 주는 공정, 이 반도체층 위에 제2절연층을 형성시켜 주는 공정, 이 제2절연층 위에 평탄화막을 형성시켜 주는 공정, 이방성에칭으로 상기 평탄화막을 제거함으로서 상기 접점구멍(23)내에 남겨진 평탄막 부분에 의해 상기 접점구멍(23)이 채워지도록 해 주는 공정, 상기 이방성에칭에 의해 노출되어진 제2절연층을 제거해 주는 공정, 상기 구조물의 전면에 제2도전층을 형성시켜 주는 공정 및 이 제2도전층 및 상기 반도체층을 패터닝해서 적층구조의 배선층을 형성시켜 주는 공정으로 구성된 반도체장치의 제조방법.Forming a first conductive layer on the semiconductor substrate 18, forming a first insulating layer on the first conductive layer, and contact holes 23 on the first conductive layer on the first insulating layer. To form a semiconductor layer on the first insulating layer 22 through which the contact hole 23 is drilled, to form a second insulating layer on the semiconductor layer, and to form the second insulating layer. A process of forming a planarization film thereon; a process of removing the planarization film by anisotropic etching so that the contact hole 23 is filled by a portion of the planar film remaining in the contact hole 23; and an agent exposed by the anisotropic etching 2) a step of removing the insulating layer, a step of forming a second conductive layer on the entire surface of the structure, and a step of patterning the second conductive layer and the semiconductor layer to form a wiring layer having a laminated structure. Method. 제1항에 있어서, 상기 반도체층을 형성시켜 준 뒤에 이 반도체층위에 실리사이드층(28)을 형성시켜 주는 공정이 포함되어 이 공정에서 형성된 이 실리사이드층(28)위에 상기 제2절연층을 형성시켜 주도록 된 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, further comprising forming a silicide layer 28 on the semiconductor layer after forming the semiconductor layer, thereby forming the second insulating layer on the silicide layer 28 formed in this process. A method for manufacturing a semiconductor device, characterized in that to give. 제2항에 있어서, 상기 실리사이드층(28)이 실리콘과 고융점금속의 화합물로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 2, wherein said silicide layer (28) is made of a compound of silicon and a high melting point metal. 제1항에 있어서, 상기 제1전도층이 상기 반도체기판(18)의 표면영역중에 형성되면서 반도체기판(18)과 반대되는 도전형으로된 불순물층(21)으로 된 것을 특징으로 하는 반도체장치의 제조방법.2. The semiconductor device according to claim 1, wherein the first conductive layer is formed in the surface region of the semiconductor substrate 18 and is made of an impurity layer 21 having a conductivity type opposite to that of the semiconductor substrate 18. Manufacturing method. 제1항에 있어서, 상기 반도체기판(18)위에 절연층으로 소자분리영역(19)을 형성시켜 주는 공정이 포함되면서, 상기 제1전도층이 이 절연층위에 형성되는 폴리실리콘층(30)으로 된 것을 특징으로 하는 반도체장치의 제조방법.2. The polysilicon layer 30 according to claim 1, comprising a step of forming a device isolation region 19 as an insulating layer on the semiconductor substrate 18, wherein the first conductive layer is formed on the insulating layer. A method of manufacturing a semiconductor device, characterized by the above-mentioned. 제1항에 있어서, 상기 반도체층이 상기 반도체기판(18)과 같은 도전형으로 된 불순물을 함유하는 폴리실리콘층(24)으로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer is made of a polysilicon layer (24) containing impurities of the same conductivity type as said semiconductor substrate (18). 제1항에 있어서, 상기 평탄화막이 폴리실리콘층(26)으로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said planarization film is made of a polysilicon layer (26). 제1항에 있어서, 상기 제2전도층이 알미늄을 함유한 금속배선층(27)으로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein said second conductive layer is made of a metal wiring layer (27) containing aluminum. 제1도전형의 반도체기판(18) 주표면에 소자분리영역(19)을 형성시켜 주는 공정과, 이 소자분리영역(19)에서 분리된 소자영역 및 상기 반도체기판(18)의 표면영역에 제2도전형 불순물층(21)을 형성시켜주는 공정,이 구조물 전면에 제 1 절연층에다가 상기 불층물층(21)위로 접점구멍(23)을 뚫어주는 공정, 이 접점구멍(23)이 뚫려진 제1절연층위에 반도체층을 형성시켜 주는 공정, 이 반도체층위에 제2절연층을 형성시켜 주는 공정, 이 제2절연층위의 전면에 평탄화막을 형성시켜 주는 공정, 이방성 에칭으로 상기 평탄화막을 제거해줌으로서 상기 접점구멍(23)내에 남아 있는 평탄막에 의해 상기 접점구멍(23)이 채워지도록 해주는 공정, 상기 이방성에칭에 의해 노출되어진 제2절연층을 제거해 주는 공정, 이 구조물 전면에 도전층을 형성시켜 주는 공정 및 상기 도전층 및 상기 반도체층을 패터닝해서 배선층을 형성시켜 주는 공정으로 구성된 반도체장치의 제조방법.Forming a device isolation region 19 on the main surface of the semiconductor substrate 18 of the first conductivity type, and removing the device region separated from the device isolation region 19 and the surface region of the semiconductor substrate 18. Forming a two-conductive impurity layer (21), drilling a contact hole (23) in the first insulating layer on the entire surface of the structure, and forming a contact hole (23) on the insulative layer (21); (1) forming a semiconductor layer on the insulating layer, forming a second insulating layer on the semiconductor layer, forming a planarizing film on the entire surface of the second insulating layer, and removing the planarizing film by anisotropic etching. A step of filling the contact hole 23 by the flat film remaining in the contact hole 23, a process of removing the second insulating layer exposed by the anisotropic etching, and forming a conductive layer on the entire surface of the structure Giving process and above figure The method of the layer and a semiconductor device consisting of a process, which by forming a wiring layer by patterning the semiconductor layer. 제9항에 있어서, 상기 반도체층을 형성시켜 주는 공정뒤에 이 공정에서 형성된 이 반도체층 위에다 실리사이드층(28)을 형성시켜 주는 공정이 포함되면서, 이 공정에서 형성된 실리사이드층(28)위에 제2절연층을 형성시켜 주도록 된 것을 특징으로 하는 반도체장치의 제조방법.10. The method of claim 9, further comprising a step of forming a silicide layer 28 on the semiconductor layer formed in the step after the step of forming the semiconductor layer, wherein a second insulating layer is formed on the silicide layer 28 formed in this step. A method for manufacturing a semiconductor device, characterized in that to form a layer. 제10항에 있어서, 상기 실리사이드층(28)이 실리콘과 고융점 금속의 화합물로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 10, wherein said silicide layer (28) is made of a compound of silicon and a high melting point metal. 제9항에 있어서, 상기 반도체층이 폴리실리콘층(24)으로 된 것을 특징으로 하는 반도체장치의 제조방법.10. The method of manufacturing a semiconductor device according to claim 9, wherein said semiconductor layer is made of a polysilicon layer (24). 제9항에 있어서, 상기 평탄화막이 폴리실리콘층(26)으로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 9, wherein said planarization film is made of a polysilicon layer (26). 제9항에 있어서, 상기 도전층이 알미늄을 함유한 금속배선층(27)으로 된 것을 특징으로 하는 반도체 장치의 제조방법.10. The method of manufacturing a semiconductor device according to claim 9, wherein said conductive layer is made of a metal wiring layer (27) containing aluminum. 제1절연층(19)위에 제1전도층을 형성시켜 주는 공정과, 그 전면에 제2절연층을 형성시켜 주는 공정, 이 제2절연층에다 상기 제1도전층위로 접점구멍(23-2)을 뚫어주는 공정, 이 접점구멍(23-2)이 뚫려진 제2절연층위에 반도체층을 형성시켜 주는 공정, 이 반도체층위에 제3절연층을 형성시켜 주는 공정, 이 제3절연층위의 전면에 평탄화막을 형성시켜 주는 공정, 이방성에칭으로 상기 평탄화막을 제거해줌으로서 상기 접점구멍(23-2)내에 남아 있는 평탄화막에 의해 상기 접점구멍(23-2)이 채워지도록 해주는 공정, 상기 이방성에칭에 의해 노출되어진 제3절연층을 제거해 주는 공정, 이 구조물 전면에 제2전도층을 형성시켜 주는 공정 및 상기 제2도전층 및 상기 반도체층을 패터닝해서 적층구조의 배선층을 형성시켜 주는 공정으로 구성된 반도체장치의 제조방법.Forming a first conductive layer on the first insulating layer 19, and forming a second insulating layer on the entire surface thereof, and contact holes 23-2 on the first conductive layer in the second insulating layer. ), A step of forming a semiconductor layer on the second insulating layer through which the contact hole 23-2 is drilled, a step of forming a third insulating layer on the semiconductor layer, Forming a planarization film on the entire surface; removing the planarization film by anisotropic etching so that the contact hole 23-2 is filled by the planarization film remaining in the contact hole 23-2; Removing the third insulating layer exposed by the step; forming a second conductive layer on the entire surface of the structure; and forming a wiring layer having a laminated structure by patterning the second conductive layer and the semiconductor layer. Manufacturing Method of Semiconductor Device . 제15항에 있어서, 상기 반도체층을 형성시켜 주는 공정뒤에 이 공정에서 형성된 반도체층위에다 실리사이드층(28)을 형성시켜 주는 공정이 포함되면서 이 공정에서 형성된 실리사이드층(28)위의 상기 제3 절연층을 형성시켜 주도록 된 것을 특징으로 하는 반도체장치의 제조방법.The third insulating layer on the silicide layer 28 formed in the process of claim 15, further comprising a step of forming the silicide layer 28 on the semiconductor layer formed in the process after the process of forming the semiconductor layer. A method for manufacturing a semiconductor device, characterized in that to form a layer. 제16항에 있어서, 상기 실리사이드층(28)이 실리콘과 고융점 금속의 화합물로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 16, wherein said silicide layer (28) is made of a compound of silicon and a high melting point metal. 제15항에 있어서, 상기 반도체층이 불순물을 함유한 폴리실리콘층(24)으로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 15, wherein said semiconductor layer is made of a polysilicon layer (24) containing impurities. 제15항에 있어서, 상기 평탄화막이 폴리실리콘층(26)으로 된 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 15, wherein said planarization film is made of a polysilicon layer (26). 제15항에 있어서, 상기 제2전도층이 알미늄을 함유하는 금속배선층(27-1)으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 15, wherein said second conductive layer is made of a metal wiring layer (27-1) containing aluminum. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880006507A 1987-05-29 1988-05-28 Manufacturing method of semiconductor device KR910007099B1 (en)

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US4800176A (en) 1989-01-24

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