KR910019147A - Dip etching treatment method before etching of polysilicon layer - Google Patents

Dip etching treatment method before etching of polysilicon layer Download PDF

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Publication number
KR910019147A
KR910019147A KR1019900005007A KR900005007A KR910019147A KR 910019147 A KR910019147 A KR 910019147A KR 1019900005007 A KR1019900005007 A KR 1019900005007A KR 900005007 A KR900005007 A KR 900005007A KR 910019147 A KR910019147 A KR 910019147A
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KR
South Korea
Prior art keywords
polysilicon layer
etching
dip
treatment method
method before
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Application number
KR1019900005007A
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Korean (ko)
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KR930000912B1 (en
Inventor
이경태
이청행
승병희
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김광호
삼성전자 주식회사
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Priority to KR1019900005007A priority Critical patent/KR930000912B1/en
Publication of KR910019147A publication Critical patent/KR910019147A/en
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Publication of KR930000912B1 publication Critical patent/KR930000912B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

내용 없음No content

Description

폴리실리콘층의 에칭전 Dip에칭 처리방법Dip etching process before etching of polysilicon layer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (가)∼(사)는 본 발명에 따른 폴리실리콘층의 에칭전 Dip에칭처리 방법을 설명하기 위한 반도체 장치의 단면도이다.2A to 2G are cross-sectional views of a semiconductor device for explaining a method of pre-etching Dip etching of a polysilicon layer according to the present invention.

Claims (2)

실리콘기판(1)상에 실리콘산화막(2)과 폴리실리콘층(3)을 차례로 형성하여 마스크(4)로 마스킹하고, 불순물을 침투시킨 다음 Dip에칭처리하며, 이어 폴리실리콘층(3)을 에칭하는 CMOS의 제조방법에 있어서, 상기 폴리실리콘층(3)의 에칭전 Dip에칭후에 2차로 BHF 감광액을호 한번 더 Dip에칭을 실시하여 1회 Dip에칭에서 폴리실리콘층(3)의 막질 위에 잔류하거나 자연적으로 자라는 산화막 등 미립자를 완전히 제거한 다음 폴리실리콘층(3)을 에칭하는 것을 특징으로 하는 폴리실리콘층의 에칭전 Dip에칭 처리방법.The silicon oxide film 2 and the polysilicon layer 3 are sequentially formed on the silicon substrate 1, masked with a mask 4, the impurities are infiltrated and then dip-etched, and then the polysilicon layer 3 is etched. In the method of manufacturing a CMOS, Dip etching of the BHF photoresist is performed once more after the dip etching before the etching of the polysilicon layer 3, and remaining on the film quality of the polysilicon layer 3 in one dip etching. A method for treating Dip etching before etching of a polysilicon layer, wherein the polysilicon layer (3) is etched after removing the fine particles such as the naturally grown oxide film completely. 제1항에 있어서, BHF감광액이 NH4F4와 HF가 6:1 또는 10:1의 비로 혼합된 혼합물임을 특징으로 하는 폴리실리콘층의 에칭전 Dip에칭 처리방법.The method of claim 1, wherein the BHF photoresist is a mixture of NH 4 F 4 and HF in a ratio of 6: 1 or 10: 1. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900005007A 1990-04-11 1990-04-11 Patterning method of poly-silicone KR930000912B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900005007A KR930000912B1 (en) 1990-04-11 1990-04-11 Patterning method of poly-silicone

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900005007A KR930000912B1 (en) 1990-04-11 1990-04-11 Patterning method of poly-silicone

Publications (2)

Publication Number Publication Date
KR910019147A true KR910019147A (en) 1991-11-30
KR930000912B1 KR930000912B1 (en) 1993-02-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900005007A KR930000912B1 (en) 1990-04-11 1990-04-11 Patterning method of poly-silicone

Country Status (1)

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KR (1) KR930000912B1 (en)

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Publication number Publication date
KR930000912B1 (en) 1993-02-11

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