Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사filedCritical문정환
Priority to KR1019900004994ApriorityCriticalpatent/KR910019136A/en
Publication of KR910019136ApublicationCriticalpatent/KR910019136A/en
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 공정순서이다. 도면의 주요부분에 대한 부호의 설명 1 : Si기판 2.4 : 산화막 3 : BPSG 5 : 금속1 is a process sequence of the present invention. Explanation of symbols for the main parts of the drawings 1: Si substrate 2.4: Oxide film 3: BPSG 5: Metal
Claims (1)
si기판(1)위에 산화막(2)과 BPSG(3)가 형성된 것에 있어서, 습식에치와 건식에치로 콘택트를 형성하고 RTP어닐을 100-1200℃에서 60초 이내로O2+Ar 혹은 O2+N2분위기에서 실시하여 BPSG(3)위에 B.P가 포함된 산화막(4)을 형성하며 HF 용액으로 습식 세척을 실시하여 산화막(4) 제거후 금속(5)을 증착시킴을 특징으로 하는 반도체 제조방법.In the formation of the oxide film 2 and the BPSG 3 on the si substrate 1, a contact is formed by wet etching and dry etching, and the RTP annealing is performed at 100-1200 ° C. within 60 seconds at O 2 + Ar or O 2 +. A method of manufacturing a semiconductor comprising forming an oxide film (4) containing BP on a BPSG (3) by carrying out in an N 2 atmosphere and performing wet cleaning with an HF solution to deposit the metal (5) after removing the oxide film (4). .※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.