KR910013955A - General purpose signal transceiver circuit pack for electronic exchange - Google Patents

Abstract

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Description

Universal Signal Transceiver Circuit Pack for Battery Exchanger

As this is a public information case, the full text was not included.

1 is a block diagram showing the configuration of the present invention,

2 is a block diagram showing the configuration of the TD-bus interface block of the present invention;

3 is a block diagram showing a configuration of a control block of the present invention.

Claims (6)

A signal service device for an electronic switch, comprising: a TD-bus interface block (3) for selecting one of two TD-buses connected to two LSPs (1) and (2), a control block (4) for controlling a signal service function; In accordance with the control of the control block (4), the sanding block (5) for generating the specified PCM signal data for each channel to the SHW interface block (6), and among the various signal service functions under the control of the control block (4) A receiving block 8 which selects a function mode to receive and detect serial data of the PCMized signal information input from the TSU 7 through the SHW interface block S, and notifies the control block 4; A general-purpose signal transceiving circuit pack for an electronic exchange comprising: a SHW interface block (6) for transmitting and receiving PCM data to and from the TSU (7). The configuration of the TD-bus interface block (3) according to claim 1, wherein the TD-bus interface block (3) comprises a DLDR circuit (10), (11) and two LSPs (1) to which TD-buses are input from two LSPs (1) and (2), respectively. In series or in parallel between the TD-bus selection circuit 12, which selects one of the TD-bus inputs from (2), and the DLDR 10, 11 and the common I / O RAM 14; The P / S and S / P conversion circuit 13 to convert, the board selection and radio signal generation circuit 15 for communication with the LSPs 1 and 2, the TD-bus interface 3 and the control block (4) the common I / O RAM control circuit 16 for controlling the common I / O RAM and the dual port common I / O RAM 14 storing various data for communication between A general purpose signal transceiving circuit pack for an electronic exchange consisting of state registers (17) for collecting faults or alarms to indicate the operating state. The configuration of the control block (4) according to claim 1, wherein the control block (4) comprises a single chip microcontroller (20) for controlling and confirming signal service functions, a clock generator (21) for supplying a clock frequency, and a single chip microcontroller ( The EP ROM 22 storing the program of 20), the S / R control circuit 23 controlling the transmission and reception of data, and the reset in which the program reset functions in the system and the single-chip microcontroller 20. A general-purpose signal transceiver circuit pack for an electronic exchange consisting of a circuit (24) and I / O decoders (25) for accessing all circuits in a system. 2. The structure of claim 1, wherein the configuration of the sending block 5 comprises: an S-RAM 32 for temporarily storing channel information and signal digit information input from the control block 4 through the latch 31; Controls the output of EPM 33, which stores sampled signal data such as R2MFC signals, DTMF signals, and continuity test tones, P / S arcs 34 that convert parallel data in series, and outputs PCMized data. PCM data output control circuit 35, RAM address control circuit 36 for controlling the input / output address of SRAM 32, counter circuit 37 and test circuit 38 for confirming normal operation. General purpose signal transmission / reception circuit pack for electronic exchange. 2. The structure of the receiving block (8) according to claim 1, wherein the configuration of the receiving block (8) is connected to each DSP and DSP (40) (41) for receiving and detecting each channel by R2MFC signal MTMF signal and continuity test tone high speed processing. EP rooms 42, 43, 44 and 45 which store byte signal detection algorithms, and PCM data input circuits 46 which distribute PCM input data from the SHW interface block S. General-purpose for an electronic exchange consisting of a clock generator (47) for supplying a clock signal and two I / O memories (48, 49) for receiving function information of the control block (4) or for outputting detected digital information. Signal Transceiver Circuit Pack. 2. The SHW interface block 6 according to claim 1, wherein the configuration of the SHW interface block 6 includes: a SHW 52 composed of a transmission Dx line and a reception Dr line through a DLDR circuit 51 for a stable SHW interface with the TSU 7, A mode selection circuit 53 for selecting one of the lines of the plurality of SHWs 52 or a channel group, an FS / CLK supply circuit 54 for receiving and supplying an FS and a clock frequency from the TSU 7, A general-purpose signal transceiver circuit pack for an electronic exchange comprising loop back control circuits (55) for looping back PCM signal data transmitted for each channel from a sending block (5) to a receiving block (8). ※ Note: The disclosure is based on the initial application.