KR910013727A - Latch malfunction prevention circuit - Google Patents

Latch malfunction prevention circuit Download PDF

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Publication number
KR910013727A
KR910013727A KR1019890020214A KR890020214A KR910013727A KR 910013727 A KR910013727 A KR 910013727A KR 1019890020214 A KR1019890020214 A KR 1019890020214A KR 890020214 A KR890020214 A KR 890020214A KR 910013727 A KR910013727 A KR 910013727A
Authority
KR
South Korea
Prior art keywords
latch
transistors
flowing
prevention circuit
current
Prior art date
Application number
KR1019890020214A
Other languages
Korean (ko)
Other versions
KR920010211B1 (en
Inventor
유영익
이창현
박시홍
주호걸
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020214A priority Critical patent/KR920010211B1/en
Publication of KR910013727A publication Critical patent/KR910013727A/en
Application granted granted Critical
Publication of KR920010211B1 publication Critical patent/KR920010211B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음.No content.

Description

래치의 오동작 방지회로Latch malfunction prevention circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 래치의 오동작 방지회로를 나타낸 상세 회로도,2 is a detailed circuit diagram showing a malfunction preventing circuit of a latch of the present invention;

제5도는 본 발명의 래치의 오동작 방지회로의 온도변화에 따른 출력변화를 나타낸 입출력 파형도이다.5 is an input / output waveform diagram showing an output change according to a temperature change of a malfunction prevention circuit of a latch of the present invention.

Claims (2)

입력되는 공급전원(Vcc)에 의하여 래치되는 래치부(1)와, 상기 래치부(1)의 래칭상태를 반전시켜 출력시키는 래치출력부(2)와,로 구성된 래치회로에 있어서, 상기 래치부(1)의 래칭상태를 상기 래치출력부(2)에 인가되는 전위를 조절함으로서 제어하기 위한 래치제어부(3)와, 로 구성된 래치의 오동작 방지회로.A latch circuit comprising: a latch portion 1 latched by an input power supply Vcc, a latch output portion 2 for inverting and outputting a latching state of the latch portion 1; And a latch control unit (3) for controlling the latching state of (1) by adjusting a potential applied to the latch output unit (2). 제1항에 있어서, 래치제어부(3)는, 공급전원(Vcc)에 의하여 온/오프되는 트랜지스터(Q4, Q5)와, 상기 트랜지스터(Q4, Q5)의 콜렉터측에 흐르는 전류(I1)와 비례하는 전류(I2)가 콜렉터측에 흐르는 트랜지스터(Q6)와, 상기 트랜지스터(Q6)에 흐르는 전류(I2)의 비례상수를 결정하기 위한 저항(R6, R8)와, 로 구성된 전류 미러에 의하여 래치출력부(2)에 인가되는 전위를 제어하는 래치의 오동작 방지회로.The latch control section 3 is proportional to the transistors Q4 and Q5 turned on / off by the supply power supply Vcc and the current I1 flowing to the collector side of the transistors Q4 and Q5. The latch output is performed by a current mirror consisting of transistors Q6 flowing on the collector side, resistors R6 and R8 for determining the proportional constant of the current I2 flowing on the transistors Q6. A latch malfunction preventing circuit for controlling the potential applied to the unit (2). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020214A 1989-12-29 1989-12-29 Error protection circuit of latch circuit KR920010211B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020214A KR920010211B1 (en) 1989-12-29 1989-12-29 Error protection circuit of latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020214A KR920010211B1 (en) 1989-12-29 1989-12-29 Error protection circuit of latch circuit

Publications (2)

Publication Number Publication Date
KR910013727A true KR910013727A (en) 1991-08-08
KR920010211B1 KR920010211B1 (en) 1992-11-21

Family

ID=19294262

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020214A KR920010211B1 (en) 1989-12-29 1989-12-29 Error protection circuit of latch circuit

Country Status (1)

Country Link
KR (1) KR920010211B1 (en)

Also Published As

Publication number Publication date
KR920010211B1 (en) 1992-11-21

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