KR910010892A - Receive spurious reduction circuit of high frequency circuit - Google Patents

Receive spurious reduction circuit of high frequency circuit Download PDF

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Publication number
KR910010892A
KR910010892A KR1019890017694A KR890017694A KR910010892A KR 910010892 A KR910010892 A KR 910010892A KR 1019890017694 A KR1019890017694 A KR 1019890017694A KR 890017694 A KR890017694 A KR 890017694A KR 910010892 A KR910010892 A KR 910010892A
Authority
KR
South Korea
Prior art keywords
circuit
switches
high frequency
cpu
spurious reduction
Prior art date
Application number
KR1019890017694A
Other languages
Korean (ko)
Other versions
KR920006131B1 (en
Inventor
라상택
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890017694A priority Critical patent/KR920006131B1/en
Publication of KR910010892A publication Critical patent/KR910010892A/en
Application granted granted Critical
Publication of KR920006131B1 publication Critical patent/KR920006131B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)
  • Transceivers (AREA)

Abstract

내용 없음.No content.

Description

고주파 회로의 수신 스퓨리어스 저하 회로Receive spurious reduction circuit of high frequency circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 구성도.2 is a block diagram of the present invention.

Claims (1)

일정한 수신 주파수 대역을 갖는 RF 수신 회로에 있어서, 안테나로부터 수신 주파수 대역의 1/2을 대역통과시키는 제1, 제2대역통과필터(36,37), 상기 안테나와 상기 제1, 제2대역통과필터(36,37) 사이에 각각 연결된 제1, 제2스위치(32,33), 상기 제1, 제2대역통과필터(36,37)의 출력 라인에 각각 연결된 제3, 제4스위치(34,35), CPU에 연결되어 상기 제2, 제4스위치(33,35)가 상기 CPU로부터 제어되도록 제어 데이타를 전송하는 제1제어라인(38), 상기 CPU에 연결되어 상기 제1, 제3스위치(32,34)가 상기 CPU로부터 제어되도록 제어 데이타를 전송하는 제2제어라인(39), 및 상기 제3, 제4스위치(34,35)에 연결된 출력라인으로 구성된 것을 특징으로 하는 고주파 회로의 수신 스퓨리어스 저하회로.An RF receiving circuit having a constant reception frequency band, comprising: first and second band pass filters 36 and 37 for band-passing half of the reception frequency band from an antenna, the antenna and the first and second band pass First and second switches 32 and 33 connected between the filters 36 and 37, respectively, and third and fourth switches 34 connected to output lines of the first and second band pass filters 36 and 37, respectively. 35, a first control line 38 connected to a CPU to transmit control data so that the second and fourth switches 33 and 35 are controlled from the CPU, and connected to the CPU. A high frequency circuit comprising a second control line 39 for transmitting control data so that the switches 32 and 34 are controlled by the CPU, and an output line connected to the third and fourth switches 34 and 35. Receive spurious reduction circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890017694A 1989-11-30 1989-11-30 Circuit for eliminating spurious signals in high frequency receiver KR920006131B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890017694A KR920006131B1 (en) 1989-11-30 1989-11-30 Circuit for eliminating spurious signals in high frequency receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890017694A KR920006131B1 (en) 1989-11-30 1989-11-30 Circuit for eliminating spurious signals in high frequency receiver

Publications (2)

Publication Number Publication Date
KR910010892A true KR910010892A (en) 1991-06-29
KR920006131B1 KR920006131B1 (en) 1992-07-31

Family

ID=19292429

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890017694A KR920006131B1 (en) 1989-11-30 1989-11-30 Circuit for eliminating spurious signals in high frequency receiver

Country Status (1)

Country Link
KR (1) KR920006131B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100355977B1 (en) * 1994-11-21 2002-12-16 소니 가부시끼 가이샤 Method and Apparatus for Transmitting an Intermittent Signal in a Radio Communication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100355977B1 (en) * 1994-11-21 2002-12-16 소니 가부시끼 가이샤 Method and Apparatus for Transmitting an Intermittent Signal in a Radio Communication

Also Published As

Publication number Publication date
KR920006131B1 (en) 1992-07-31

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