KR950022216A - Frequency common communication system terminal - Google Patents
Frequency common communication system terminal Download PDFInfo
- Publication number
- KR950022216A KR950022216A KR1019930030690A KR930030690A KR950022216A KR 950022216 A KR950022216 A KR 950022216A KR 1019930030690 A KR1019930030690 A KR 1019930030690A KR 930030690 A KR930030690 A KR 930030690A KR 950022216 A KR950022216 A KR 950022216A
- Authority
- KR
- South Korea
- Prior art keywords
- received signal
- communication system
- control unit
- system terminal
- unit
- Prior art date
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- Transceivers (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
본 발명은 주파수 공용통신 시스템 단말기에 관한 것으로, 특히 단말기의 송신출력을 수신신호 강도에 따라 증가 또는 감소시켜 베터리의 소모를 줄일 수 있도록 한 주파수 공용통신 시스템 단말기에관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency common communication system terminal, and more particularly, to a frequency common communication system terminal that can reduce battery consumption by increasing or decreasing the transmit power of a terminal according to a received signal strength.
이를 위하여 안테나(11), 주파수합성부(13),수신부(13),음성처리 및 제어부 (15)송신부(14)를 갖는 주파수공용통신 시스템 단말기에 있어서, 상기 음성처리 및 제어부(15)및 수신부(12)사이에 연결되어 수신한 신호의 세기를 알려주는 수신신호강도 검출부(18)와, 상기 음성처리 제어부(15)및 송신부(14)사이에 연결되어 수신신호의 세기에 따란 송신출력의 크기를 조정하는 송신출력 제어부(19)를 포함한여 구성된 것이다.To this end, in the common frequency communication system terminal having an antenna (11), a frequency synthesizer (13), a receiver (13), a voice processor and a control unit (15), the voice processor and control unit (15) and a receiver unit. A received signal strength detection unit 18 connected between the signals 12 and the received signal strength detector 18 to inform the strength of the received signal, and a size of the transmission output depending on the strength of the received signal connected between the voice processing control unit 15 and the transmitter 14; It comprises a transmission output control unit 19 for adjusting the.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 주파수 공용통신 시스템 단말기의 블럭도.2 is a block diagram of a frequency common communication system terminal according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930030690A KR950022216A (en) | 1993-12-29 | 1993-12-29 | Frequency common communication system terminal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930030690A KR950022216A (en) | 1993-12-29 | 1993-12-29 | Frequency common communication system terminal |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950022216A true KR950022216A (en) | 1995-07-28 |
Family
ID=66853626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930030690A KR950022216A (en) | 1993-12-29 | 1993-12-29 | Frequency common communication system terminal |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950022216A (en) |
-
1993
- 1993-12-29 KR KR1019930030690A patent/KR950022216A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |