KR910010307A - RAM error detection circuit - Google Patents

Abstract

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Description

RAM Error Detection Circuit

As this is a public information case, the full text was not included.

2 is a circuit diagram according to the present invention.

Figure 3a or RAM control signal waveform diagram of a microprocessor.

3b is a waveform diagram of an output signal according to the present invention;

Claims (6)

In a circuit for detecting a RAM (RAM) error in a system consisting of a microprocessor (11) and a RAM (RAM: 10) connected to the microprocessor (11) via a data bus and an address bus; Reading of the microprocessor 11 ( ) And write ( A first AND gate 23 connected to a terminal) and logically ANDing the two input signals, and a first temporarily connected to an output terminal of the address bus and the first AND gate 23 to temporarily perform address storage. A second latch circuit 22 connected to the latch circuit 21, an output terminal of the data bus and the first AND gate 23 to temporarily store data, and the first AND gate 23 and the microcomputer. Read of processor ( Terminal is connected to the output terminal of the AND gate 23 and the inversion signal and the read control signal (AND) of the output enable terminal (RAM) of the RAM (10) And an address input terminal to a second AND gate 25 to be applied to the microprocessor 11 and an address bus on the side of the microprocessor 11, and a control input terminal to an output terminal of the first AND gate 23. A first three-state buffer 12 having an output terminal connected to an address bus on the side of (10), an input terminal connected to an output terminal of the first latch circuit 21, and an output terminal of the first AND gate 23; A second three-state buffer 13 having an output terminal connected to an address bus on the RAM 10 side, and a data input terminal on a data bus on the RAM 10 side; Read of microprocessor (11) The control input terminal is connected to the terminal, and the data input terminal is connected to the data bus of the microprocessor 11 side, and the write of the microprocessor 11 is performed. A fourth tri-state buffer 15 having a control input terminal connected to the terminal and an output terminal connected to a data bus on the RAM 10 side, and a signal input terminal connected to the second latch circuit 22. A fifth tri-state buffer 16 having a control input terminal connected to an output terminal of the first AND gate, and a data input terminal connected to a data bus data bus of the RAM 10 side, and the first AND gate 23 connected to the data bus data bus. A sixth tri-state buffer 17 having a control input terminal connected to an output terminal of the sixth three-state buffer 17 and a fifth three-state buffer 16 and a sixth three-state buffer 17 for exclusively ORing the two inputs. An exclusive OR gate 20, a divider 19 for dividing and outputting a clock frequency fs by a predetermined number N, and a RAM select terminal of the microprocessor 11 ( ) And the chip select terminal of the RAM 10 by performing a logical product on two input signals connected to the divider 19. A seventh three-state buffer (2) connected to a second AND gate 24 for outputting to the output terminal of the exclusive OR gate 20 and a control input terminal to the divider 19. 18) and an OR gate (26) connected to the output stages of the dispensing unit (19) and the seventh tri-state buffer (18). 2. The first latch circuit (21) of claim 1, wherein the first latch circuit (21) sends an address signal through the second tri-state buffer (14) when the microprocessor (11) does not control the RAM (10). RAM error detection circuit, characterized in that applied to the terminal (Ai). The control circuit of claim 1, wherein the third tri-state buffer 14 and the fourth tri-state buffer 15 are connected to a control signal of the microprocessor 11. , To control the data direction according to the ), The third three-state buffer 14 is turned ON and the write control signal RAM error circuit, characterized in that the fourth three-state buffer (15) is ON. The method of claim 1, wherein the second latch circuit 22 is a RAM (10) control signal of the microprocessor (11) , If either signal is active, the most recent read or written data is stored and the two signals ( , Are all high, the RAM error detection circuit is disabled and stores the latched data regardless of the input signal. The RAM of claim 1, wherein the exclusive OR gate 20 compares data most recently latched to the second latch circuit 22 with data output from the RAM 10. Air detection circuit. The RAM error signal of claim 1, wherein the OR gate 26 logically combines an inverted signal of the output of the seventh tri-state buffer 18 and a divided signal of the divider 19. A RAM error detection circuit which outputs (Pi). ※ Note: The disclosure is based on the initial application.