KR910009487Y1 - Initial reservation circuit of PLL tuner - Google Patents

Initial reservation circuit of PLL tuner Download PDF

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Publication number
KR910009487Y1
KR910009487Y1 KR2019860021661U KR860021661U KR910009487Y1 KR 910009487 Y1 KR910009487 Y1 KR 910009487Y1 KR 2019860021661 U KR2019860021661 U KR 2019860021661U KR 860021661 U KR860021661 U KR 860021661U KR 910009487 Y1 KR910009487 Y1 KR 910009487Y1
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circuit
transistor
flip
pll
flop
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KR2019860021661U
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KR880013896U (en
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박생기
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주식회사 금성사
구자학
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
    • H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

내용 없음.No content.

Description

PLL튜너의 초기 예약 회로Initial reservation circuit of PLL tuner

제1도는 본 고안의 초기예약 회로도.1 is an initial reservation circuit of the present invention.

제2도는 본 고안의 타실시예의 회로도.2 is a circuit diagram of another embodiment of the present invention.

제3도는 제1도의 각부 파형도.3 is a waveform diagram of each part of FIG.

제4도는 제2도의 각부파형도.4 is an angular waveform diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 지연회로 20 : 포지티브에지검출회로10: delay circuit 20: positive edge detection circuit

30 : PLL합성회로 FF : 플립플롭30: PLL synthesis circuit FF: flip flop

SW1, SW2: 스위치 Q1, Q2; 트랜지스터SW 1 , SW 2 : switch Q 1 , Q 2 ; transistor

C1-C4: 콘덴서 R1-R6: 저항C 1 -C 4 : Capacitor R 1 -R 6 : Resistance

D1-D3: 다이오드 G1, G2, G3: 낫드 게이트D 1 -D 3 : Diode G 1 , G 2 , G 3 : Naked Gate

G : 낸드 게이트G: NAND gate

본 고안은 PLL(Phase laded loop)튜너의 예약 프로그램에 관한 것으로서, 청취자가 미리 예약한 방송을 선국하여 청취할수 있게 한것에 주안점을 둔 것이다.The present invention relates to a reservation program of a PLL (Phase Laded Loop) tuner, and focuses on allowing a listener to tune in to a previously reserved broadcast.

종래에는 전원을 오프하기 전에 청취하고 있던 박송을 전원을 온시키므로서 전에 청취하고 있던 방송을 청취 하게 되어 있으며, 최근 일본국 NEC사에서의 4비트 마이크로 컴퓨터를 내장한 μPD1704-01325하는 PLL튜너 집적회로에 프로그램이라는 기능이 있으며 이는 5국까지 예약 할수 있는데, 전원을 온, 오프시마다 채널5국이 번갈아 모두 1국씩 바꾸어지기 때문에 잠깐 사이에 전원을 5번 켜면 방송이 5번 바꾸어지는 문제점을 가지고 있으므로 그 기능을 사용하지 못하는 입장이 있다.Conventionally, the PLL tuner integrated circuit, which is a µPD1704-01325 with a 4-bit microcomputer built by NEC of Japan, is used to listen to broadcasts that have been previously listened to by turning on the power that was listening before turning off the power. There is a program function, which can be reserved up to 5 stations. When the power is turned on and off, the channel 5 stations are switched one by one every time, so if you turn on the power 5 times for a short time, the broadcast changes 5 times. There is a position that can not use the function.

본 고안은 상기와같은 종래의 결점을 해소하고자 필요로 하는 방송을 먼저 예약시켰다가 청취할수 있게 한것으로서, 이를 첨부도면에 따라서 설명하연 다음과 같다.The present invention is to make a reservation for the first broadcast to listen to the need to solve the above-mentioned drawbacks, as described in accordance with the accompanying drawings as follows.

제1도에 도시한 바와같이 프로그램스위치(S1)에서 콘텐서(C1)를 통해 저항(R1)과 플랩플릅(FF)의 셋트단자(S)에 접속하고, 다이오드(D1)오 트랜지스터(Q1)와 저항(R2)을 통해 콘덴서(C3)와 플립플롭(FF)의 클럭단자(C)에 접속하여, 플립플롭(FF)의 출력단자(Q)의 신호에 의해서 다이오드(D3)와 저항(R5)을 거쳐 스위칭 트랜지스터(Q2)가 구동되도록 수동선택스위치(S2)론 접속시킨 공지의 PLL 합성회로(30)에 트랜지스터(Q2)를 접속 한다.As shown in FIG. 1, the program switch S 1 is connected to the set terminal S of the resistor R 1 and the flap FF through the capacitor C 1 , and the diode D 1 . It is connected to the clock terminal C of the capacitor C 3 and the flip-flop FF through the transistor Q 1 and the resistor R 2 , and is connected to the diode of the output terminal Q of the flip-flop FF. connects the transistor (Q 2) to (D 3) and a resistor (R 5) through a switching transistor (Q 2), a manual selector switch (S 2) theory PLL synthesizer circuit 30 in which connection known to be driven.

그리고 플립플롭(FF)의 출력단자(Q)에서 낫드 게이트(G1, G2)와 콘덴서(C2) 및 저항(R4)으로 구성한 지연 회로(10)를 거쳐 다이오드(D2)와 저항(R2)를 통해 트랜지스터(Q1)의 베이스에 연결하여서 된 것이다.In the output terminal Q of the flip-flop FF, a diode D 2 and a resistor are passed through a delay circuit 10 composed of a naked gate (G 1 , G 2 ), a capacitor (C 2 ), and a resistor (R 4 ). It is connected to the base of transistor Q 1 via (R 2 ).

제2도는 타실시예의 회로도로서 상기 제1도의 프로그램 스위치(S1)와 다이오드(D3)사이에 저항(R6)과 콘텐서(C4), 낫드게이트(C3) 및 낸드게이트(G4)를 구성한 포지티브에지 검출회로(20)와 인버터(G5)를 접속시켜서 스위칭 트랜지스터(Q2)를 구동할수 있게 한 것이다.FIG. 2 is a circuit diagram of another embodiment. The resistor R 6 , the capacitor C 4 , the naked gate C 3 , and the NAND gate G between the program switch S 1 and the diode D 3 of FIG. 1 . It is possible to drive the switching transistor Q 2 by connecting the positive edge detection circuit 20 constituting 4 ) and the inverter G 5 .

프로그램 스위치(S1)가 온되면 콘덴서(C1)와 저항(R1)에 의해 플립플롭(FF)의 출력(Q)에는 제3b도와 같이 "하이"를 출력시키고 그 하이레벨을 다이오드(D3)와 저항(R5)을 통해 트랜지스터(Q2)에 바이어스 전원을 걸어주므로서 트랜지스터(Q2)를 온시키고 따라서, 다이오드(D4)와 스위칭 트랜지스터(q2)를 도통시켜서 청취하고 싶은 방송이 메모리 되어 있는 스위치(S2)를 전자적으로 온시켜 미리 예약한 방송을 선국하고, 플립프릅(FF)출력(Q)의 하이신호는 데이트(G1, G2)와 저항(R4)과 콘덴서(C2)로 구성한 지연회로(10)로 입력되어 이 하이신호는 다이오드(D2)와 저항(R2)을 통하여 트랜지스터(Q1)의 베이스측에 바이어스 전원을 걸어주게 되어 트랜지스터(Q1)를 온시켜서 프로그램 스위치(S1)의 하이신호는 다이오드(D1)와 트랜지스터(Q1) 및 저항(R3)을 통해 플립플롭(FF)의 클럭단자(C)에 인가시키므로서 플립플릅(FF)의 출력단자(Q)를 로울신호로 출력시켜 트랜지스터(Q2)를 오프시키고, 출력단자 (를 하이레벨로 출력하므로서 제3c도와 같은 상태가 된다.When the program switch S 1 is turned on, a high is output to the output Q of the flip-flop FF by the capacitor C 1 and the resistor R 1 as shown in FIG. 3) and a resistor (R 5) through a transistor (q 2) biased because walking a power up turns on the transistor (q 2) and thus, the diode (D 4) and a switching transistor (q 2), the conduction by want to listen to The preset memory is tuned by turning on the switch (S 2 ) in which the broadcast is stored in memory, and the high signal of the flip-flop (FF) output (Q) is the data (G 1 , G 2 ) and the resistance (R 4 ). and the capacitor is input to the delay circuit 10 is configured to (C 2) a high signal is dropped through the diode (D 2) and a resistor (R 2) walking the bias supply to the base side of the transistor (Q 1) transistor ( high signal is a diode (D 1) by one of the Q 1) program switch (S 1) and the transistor (Q 1) and a low (R 3) because applied to the clock terminal (C) of the flip-flop (FF) via the stand to output an output terminal (Q) of the flip-peulreup (FF) to a roll signal, and turning off the transistor (Q 2), the output terminal ( Is outputted at a high level, resulting in a state similar to that of FIG. 3C.

반대로 프로그램스위치(S1)를 오프시키면 플립플롭(FF)의 동작에 의해 스위칭 트랜지스터(Q1)는 오프된다. 고리고 본 고안의 타실시예를 제2도에 따라서 설명하면, 프로그램스위치(S1)를 온시키면 저항(R6)과 콘덴서(C4), 낫드게이트(G3) 및 앤드게이트(G4)로 구성한 포지티브 에지 검출회로(20)를 통해서 하이신호로 출력시키게 되어 스위칭 트랜지스터(Q2)를 온시키므로서(제4c도와 같이)공지의 PLL합성회로(30)단자(1)에 기억시킨 방송국을 선택하게 된다.On the contrary, when the program switch S 1 is turned off, the switching transistor Q 1 is turned off by the operation of the flip-flop FF. If another embodiment of the present invention is described according to FIG. 2, turning on the program switch S 1 causes the resistor R 6 , the capacitor C 4 , the naked gate G 3 , and the end gate G 4. A broadcasting station which is outputted as a high signal through the positive edge detection circuit 20 composed of the < Desc / Clms Page number 11 > and stored in the known PLL synthesis circuit 30 terminal 1 while turning on the switching transistor Q 2 (as shown in FIG. Will be selected.

이와같이 본 고안온 PLL합성회로에 기억시킨 발송을 선국하여 청취할수 있게 되는데 만약에 PLL합성회로(30)단자(1)에 청취해야할 방송국을 메모리시켜놓고 단자(2)의 방송을 선택하여 청취하다가 전원오프시키고 그 후에 전원을 온시키면 단자(2)에 방송국이 선택되는 것이 아니라 단자(1)에 기억시킨 방송이 선택되게 되므로서 미리 예약하여 메모리시킨 방송을 선국시켜 청취할수 있게 된 유용한 것이다.In this way, the transmission stored in the PLL synthesis circuit of the present invention can be tuned and listened. If the broadcasting station to be listened to is stored in the PLL synthesis circuit 30 terminal 1, the broadcast of the terminal 2 is selected and listened to, When the power is turned off and then turned on, the broadcast station is not selected at the terminal 2, but the broadcast stored in the terminal 1 is selected.

Claims (2)

프로그램스위치(S1)와 플립플롭(FF) 및 지연회로(10)를 통해 트랜지스터(Q1)를 구동하게 연결하고 플립플롭(FF)의 출력(Q)에 공지의 PLL 튜너 합성회로(30)에 접속된 스위칭 트랜지스터(Q2)를 연결하여서 예약된 방송을 선국할 수 있게 한 것을 특징으로 하는 PLL튜너의 초기예약회로.PLL tuner synthesis circuit 30 is coupled to drive transistor Q 1 to drive through program switch S 1 and flip-flop FF and delay circuit 10 and to output Q of flip-flop FF. An initial reservation circuit of a PLL tuner, characterized in that a reserved broadcast can be tuned by connecting a switching transistor (Q 2 ) connected thereto. 제1항에 있어서, 프로그램스위치(S1)와 스위칭 트랜지스터(Q2) 사이에 포지티브 에지 검출회로(20)와 인버터(G3)를 연결하여서 된 PLL튜너의 초기예약 회로.The initial reservation circuit of a PLL tuner according to claim 1, wherein a positive edge detection circuit (20) and an inverter (G 3 ) are connected between a program switch (S 1 ) and a switching transistor (Q 2 ).
KR2019860021661U 1986-12-29 1986-12-29 Initial reservation circuit of PLL tuner KR910009487Y1 (en)

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KR2019860021661U KR910009487Y1 (en) 1986-12-29 1986-12-29 Initial reservation circuit of PLL tuner

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Application Number Priority Date Filing Date Title
KR2019860021661U KR910009487Y1 (en) 1986-12-29 1986-12-29 Initial reservation circuit of PLL tuner

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KR880013896U KR880013896U (en) 1988-08-30
KR910009487Y1 true KR910009487Y1 (en) 1991-12-09

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