KR850002135Y1 - Up-down circuit for auto turning device - Google Patents

Abstract

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Description

Tuning voltage automatic up / down circuit

1 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

100: charge and discharge circuit 200: falling side control unit

300: rising side control unit 20: constant voltage circuit

30: fully tuned tuner 40: tuned voltage terminal

50: Auto tuning circuit during normal broadcasting I ₁ : Gate

N ₁ -N ₄ : NAND gate Q ₁ -Q ₇ : Transistor

D ₁ -D ₃ : Diode D ₄ : Zener Diode

C ₁ : condenser R ₁ -R ₂₀ : resistance

The present invention provides a TV receiver having an electronic tuning tuner that selects a reception frequency based on a tuning voltage. When the tuning voltage rises in the absence of broadcast, the tuning voltage is automatically increased when the tuning voltage is higher than the tuning voltage for receiving the highest channel in the corresponding band. The present invention relates to a tuning voltage automatic up and down circuit which automatically goes down when the tuning voltage goes down and falls below the tuning voltage which receives the lowest channel in the band.

Conventionally, there has been a circuit configuration in which the tuning voltage is changed using a variable resistor to supply a tuner or automatically up and down using an expensive integrated circuit (IC). However, in the former case, a variable resistor must be manually configured. There was a hassle, and in the latter case the problem was to raise the cost of the product.

In view of the above, the present invention uses a low-cost and general NAND gate IC and transistor to easily and automatically tune up and down the tuning voltage without a broadcast. Referring to the drawings in detail as follows.

In the present invention, as shown in FIG. ₁ , the lower switch SD and the transistor Q through the NAND gate IC I ₁ and the power supply terminal 14 through the resistor R ₁ , the terminal 5, and the diode D ₂ . ₃ -Q ₅ ), the falling side control unit 200 consisting of a zener diode (D ₄ ) and a resistor (R ₁₂ -R ₁₈ ) is connected, and a resistor (R ₁₄ ) at the NAND gate IC (I ₁ ), the terminal (14). ), The terminal 8 and the diode D ₃ to connect the rising side control unit 300 consisting of the rising switch Su, the transistors Q ₆ -Q ₇ and the resistors R ₁₉ -R ₂₀ , Transistors Q ₁ -Q ₂ and resistors R ₅ -R through the junction terminals 3, 6 and the junction terminals 11, 9 and diode D _{1 of the} NAND gate IC I ₁ . ₁₁ ) and the charging and discharging circuit unit 100 including the condenser C ₁ and connecting the falling side control unit 200 and the rising side control unit 300 to the tuning voltage terminal 400 of the automatic tuning tuner 30. ), And the above-mentioned charging and discharging circuit unit 100 is connected between the constant voltage circuit 20 and the automatic tuning tuner 30. Configure

Unexplained symbol B ⁺ is a DC power supply, R ₃ , R _A , R _B are resistors, 50 is a public tuning circuit for public broadcasting, D _A , D _B , C _C are diodes, S _D and S _U are manual rising and falling side switches, respectively. Referring to the effect of the present invention configured as described above are as follows.

In FIG. 1, when the power is turned on in the absence of broadcast, the capacitor C ₁ of the charge / discharge circuit unit 100 has no charged charge, and thus, becomes 0V, and thus the transistor of the rising controller 300 Since the bias voltage is not applied to the base side of Q ₇ ) and the transistor Q ₇ is turned off, the power supply B ⁺ is applied to the base side of the transistor Q ₆ through resistors R ₁₈ and R ₂₀ . Since the transistor Q ₆ is turned on, the power supply B ⁺ is applied to the collector side through the resistor R ₂ , the resistor R ₄ , and the diode D _{3. In} this case, the power supply B ⁺ ) is the resistance (R _2), a voltage drop by the resistor (R ₄₎ since the gate IC (I ₁₎ an input terminal (1), (8), the low level (the gate IC (I ₁ a) to recognize the low The resistors R ₂ and R ₄ are set to large values).

On the other hand, since the voltage appearing at the tuning voltage terminal 40 of the fully-tuned tuner 30 is at 0 V, the zener diode D ₄ of the falling-side control unit 200 is turned off and the transistor Q ₅ is turned on. Is turned off, which causes transistor Q ₄ to be turned ON and transistor Q ₃ to be turned OFF so that no current flows to the collector side thereof. In this case, power source B ⁺ is resistor R ₃ and resistor ( The input terminals 15 and 5 of the gate IC I ₁ are input in the level state through R ₁ ). Such a circuit operation state is maintained until the zener diode D ₄ becomes a conductive state.

Therefore, since the low signal is input to the terminal _{1 of} the gate IC I ₁ described above, the high signal appears in the output terminal 3 of the NAND gate N ₁ regardless of the signal input from the terminal 2. In this case, since a high signal is input to the terminal 5, a low signal appears at the output terminal 4 of the NAND gate N ₂ , and the low signal is input to the terminal 2.

In this way, a flip-flop circuit by the NAND gates N ₁ and N ₂ is determined, and even after the signal input to the terminal ₁ of the gate IC I ₁ becomes high, Since the signal input to the terminal 2 is in a low state, the signal appearing in the terminals 3 and 6 is stable in a high state regardless of the signal input to the terminal 1. The high signal is applied to the emitter side of the transistor Q ₂ through the resistor R ₁₁ of the charge and discharge circuit unit 100, so that the emitter side is in a high state.

On the other hand, since a low signal is input to the terminal 8, a high signal appears on the output terminal 10 of the NAND gate N ₃ regardless of the signal input to the terminal 9, and is applied to the terminal 12. Since a high signal is input to the terminal 113, a low signal appears at the output terminal 11 of the NAND gate N ₄ , and the low signal is input to the terminal 9.

In this way, a flip-flop circuit is determined by the NAND gates N ₃ and N _4. Even after a signal input to the terminal 8 of the gate IC I ₁ becomes high, Since the signal input to the terminal 9 is in a low state, the signals appearing in the terminals 10 and 12 become high, and the signals appearing in the terminals 9 and 11 are stabilized in the low state. Therefore, since the low signal appears at the terminals 9 and 11, the diode D ₁ is cut off, and the bias voltage is not applied to the base side of the transistor Q ₂ of the charge and discharge circuit unit 100. transistor (Q ₂₎ is because in the OFF state, and in this case the output voltage is set by the constant voltage circuit 20 is bonap a resistance (R ₅₎ (R _6), so is applied to the base of the transistor (Q ₁₎ transistor (Q ₁ ) Becomes a conductive state, and the set voltage of the constant voltage circuit 20 starts to be charged in the capacitor C ₁ .

At this time, as the charging voltage is increased in the capacitor C ₁ , the voltage input to the tuning voltage terminal 40 of the fully tuned tuner 30 is increased, thereby increasing the reception frequency. Subsequently, when the charging voltage of the capacitor C ₁ rises, the charging voltage is applied to the base axis of the transistor Q ₇ through the resistor R ₁₉ , so that the transistor Q ₇ is conducted, which causes the transistor Q _6. ) Is OFF and no current flows to the collector side. Therefore, a high signal is input to the terminals 1 and 8 because the power supply B ⁺ does not drop voltage through the resistors R ₂ and R ₄ . .

As described above, even when the high signal is input to the terminals 1 and 8, the terminals 3 and 6 are stable in the high signal state, and the terminals 9 and 11 are stable in the low signal state. Since the transistor Q ₂ is continuously turned off and the capacitor C ₁ is in a state in which the set voltage of the constant voltage circuit 20 is continuously charged through the transistor Q ₁ , the tuning voltage terminal 40 of the automatic tuning computer 30 is maintained. The voltage input to) increases, so the receiving frequency keeps rising.

Therefore, after receiving up to the maximum frequency of the fully tuned tuner 30, since the charging voltage of the capacitor C ₁ does not need to continuously increase, the tuning voltage corresponding to the maximum frequency is set to the zener voltage of the zener diode D ₄ . Then, when the charging voltage of the capacitor C ₁ reaches the maximum frequency tuning voltage, the zener diode D ₄ is turned on so that the resistors R ₁₆ and R ₁₇ are connected to the base side of the transistor Q ₅ . a bias voltage divider as is, so the transistor (Q ₅₎ is conductive, each transistor (Q ₄₎ becomes OFF, the transistor (Q ₃₎ in the oN state since the flow whose collector side circuit power in this case (B ⁺⁾ The voltage is dropped by the resistors R ₃ and R ₁ and input to the input terminals 13 and 5 of the gate IC I ₁ in a low level state.

Therefore, since the low signal is input to the terminal 5 of the gate IC (I ₁ ), the high signal appears on the output terminal 4 of the NAND gate N ₂ regardless of the signal input to the terminal 6. In this case, the charging voltage of the capacitor C ₁ is turned on through the resistor R ₁₉ , and the transistor Q ₇ is turned on and the transistor Q ₆ is turned off, so that the terminal _{1 of the} gate IC I ₁ is turned on. ), A high signal is input, so a low signal appears at terminals 3 and 6.

Therefore, the high signal appears on the terminal 4 regardless of the signal input to the terminal 5 and is applied to the terminal 2 so that the terminals 2, 4 are in a high signal state, and the terminals 3, ( 6, the low signal state is set, and the flip-flop circuit by the NAND gate N ₁ (N ₂ ) is stabilized. At this time, since the low signal shown at the terminals 3 and 6 is applied to the emitter side of the transistor Q ₂ through the resistor ₁₁ , the emitter side is turned low.

On the other hand, since the transistor Q ₃ is in the ON state, the power supply B ⁺ is dropped by the resistor R ₃ , and a low signal is input to the terminal 13 of the gate IC I ₁ . ), A high signal is displayed, and since the transistor Q ₆ and the diode D ₃ are turned off at the terminal 8, a high signal is input and a low signal is displayed at the terminals 10 and 12. Since the signal shown in 12) is in the low state, the signal appearing in the terminals 11 and 9 is stabilized in the high state regardless of the signal of the terminal 13.

At this time, the high signal shown at the terminals 11 and 9 is applied to the base of the transistor Q ₂ through the diode D ₁ and the resistor R ₈ , so that the transistor Q ₂ is conducted so that the transistor Q _1. ) Is turned off, and the charge charged in the capacitor C ₁ begins to discharge through the collector side of the transistor Q ₂ to decrease the voltage appearing at the tuning voltage terminal 40 of the electronic tuning tutor 30. The reception frequency is also lowered.

When the charge voltage of the capacitor C ₁ decreases, the zener diode D ₄ is turned off, which causes the transistor Q ₅ to be turned off, the transistor Q ₄ is turned on, and the transistor Q ₃ is turned off. Since the same circuit operation is repeated as in the case where the initial power is turned on and the initial power is turned on, the charge of the capacitor C ₁ starts to be charged again in the OV state, and the reception frequency is raised again. Summarizing the above-described circuit operation, that is, when the initial power is turned ON, the transistor Q ₇ of the rising-side control unit 300 is turned OFF, the transistor Q ₆ is turned ON, and the terminal 3 of the gate IC I ₁ is turned on. ), (6) signals are high, terminals 9 and 11 signals are low, and transistor Q ₂ is turned off so that the charge charge of capacitor C ₁ is increased. Becomes Up.

At this time, the zener diode D ₄ of the falling-side control unit 200 is turned off, the transistors Q ₅ and Q ₃ are turned off, and the transistor Q ₄ is turned on. When the charge charge of the next capacitor C ₁ reaches the tuning voltage corresponding to the maximum reception frequency, the zener diode D ₄ is turned on, the transistor Q ₅ is turned on, the transistor Q ₄ is turned off, and the transistor Q _{3 is turned on.} ) Is ON, the terminals 5 and 13 signals of the gate IC (I ₁ ) are low, the terminals 9 and 11 signals are high, and the terminals 3 and 6 signals. Since the low and the transistor Q ₂ is turned on and the charge charge starts to be discharged in the capacitor C ₁ , the reception frequency is lowered.

At this time, the transistor Q ₇ of the rising side control unit 300 is ON and the transistor Q ₆ is OFF. Next, when the charged charge of the capacitor C ₁ is discharged and becomes almost OV, the same circuit operation as the above initial power ON is repeated, and all frequency bands are automatically turned up and down without a broadcast. -Down).

The present invention operating as described above is configured to connect the rising, falling side control unit and charge, and vibration protection circuit unit consisting of a low-cost gate IC and a transistor, the tuning voltage rises in the absence of broadcast, and receives the highest channel in the corresponding band. If the tuning voltage is higher than the tuning voltage, the tuning voltage is automatically lowered. Thus, the tuning voltage is lowered and the tuning voltage is automatically increased when the tuning voltage is lower than the tuning voltage receiving the lowest channel in the band. Cost savings are also effective. The above has described the circuit operation of the present invention in the absence of a broadcast, and the following will describe the case where the broadcast is received.

If the broadcast voltage is increased after the tuning voltage is increased, the output terminal 11 signal of the NAND gate N ₄ becomes low and the output terminal 3 signal of the NAND gate N ₁ becomes high when the tuning voltage is increased. As described above, the transistor Q ₂ is in an off state. At this time, the normal auto-tuning circuit 50 has the output A signal low, the output B signal high, and the output C signal high when there is no broadcast. The signals A), (B) and (C) become high and low.

Therefore, when the tuning voltage is increased and the broadcast is received, the output terminals B and C of the auto-tuning circuit 50 become high from low when broadcasting, respectively, and output terminals of the NAND gates N ₁ and N ₄ . The signals (3) and (11) do not affect the base of the transistor Q ₂ , and at this time, a constant voltage of the output terminal A is applied to the base of the transistor Q ₂ through the diode DA, but the transistor Since the voltage at the output terminal A is applied such that the collector current of Q ₂ is equal to the collector current of transistor Q ₁ , the charge and discharge current is not agitated in the capacitor C ₁ . The voltage is kept constant so that the broadcast signal can be continuously received.

On the other hand, when the tuning voltage is lowered and the broadcast is received, when the tuning voltage is lowered, the output terminal 11 signal of the NAND gate N ₄ is high and the output terminal 3 signal of the NAND gate N ₁ is low. As described above, the transistor Q ₂ is in the on state.

At this time, when the broadcast is received, the output terminals B and C of the auto-tuning circuit 50 become low when the broadcast signal is received. Therefore, the output terminals 11 and 3 of the NAND gates N ₄ and N ₁ are signaled. Does not affect the transistor Q ₂ , and at this time, since a constant voltage of the output terminal A is applied to the base of the transistor Q ₂ through the diode D _A , the charge / discharge current is applied to the capacitor C ₁ . Since it does not flow, the voltage of the fully automatic tuner 30 is kept constant so that it is possible to continuously receive a constant broadcast signal. If the manual up / down switch (Su, S _D ) is pressed in the broadcast reception state, a low signal is input to the terminals (E) and (D) of the auto-tuning circuit 50 during the broadcast and its output terminal (B), The signal (C) goes from low to high, and the output terminal A goes from low to a constant voltage.

Therefore, the output terminals A, B, and C appear as described above, and the transistor Q ₂ is turned on by the NAND gates N ₁ and N ₄ . It is controlled off so that the tuning voltage rises or falls until the next broadcast reception. As described above, during the automatic up and down operation during no signal, the output terminals A, B, and C of the automatic tuning circuit 50 during broadcasting become low, high, and high states, and the transistor Q _It does not affect the operation of ₂ ). In other words, the operation of the automatic tuning circuit 50 during broadcasting prevents the circuit function of the present invention from performing automatic up and down when a broadcasting signal is received and sends a constant tuning voltage to the automatic tuning tuner 30, and there is no broadcasting signal. When the user presses the manual up, down switch (Su), or (S _D ) while receiving a broadcast, the original up and down functions are performed.

In addition, the tuning voltage terminal (40 of the base and the electronic tuning tuner (30) of the transistor (Q ₇₎ through a resistor (R _19), a discharge voltage of the capacitor (C ₁₎ in addition to the collector current of the transistor (Q ₂₎ at the time of broadcast receiving This current value can be compensated for by a variable voltage constant appearing at the output terminal A of the automatic tuning circuit 50 during broadcasting, and thus normal broadcast reception can be performed.

Claims (1)

(Correct) Transistor Q ₃ -through resistor R ₁ , terminal 5 and diode D ₂ to power supply terminal 14 of gate IC I ₁ composed of NAND gates N ₁ -N ₄ . Q ₅ ), the falling-side control unit 200 composed of the zener diode D ₄ and the resistors R _12- R ₁₈ is connected, and the transistor is connected through the resistor R ₄ , the terminal 8, and the diode D ₃ . (Q ₆ -Q ₇ ) and the rising side control part 300 made of the resistors R ₁₉ -R ₂₀ are connected, and the common terminals 3 and 6 of the gate IC I ₁ and the terminal ( 11), (9), and the charge and discharge circuit portion 100 made of transistors Q ₁ -Q ₂ , resistors R ₅ -R ₁₁ , and capacitor C ₁ through the diode D ₁ , respectively, The charging and discharging circuit unit 100, the falling side control unit 200, and the rising side control unit 300 connected to the constant voltage circuit 20 are connected to the tuning voltage terminal 40 of the conventional automatic tuning tuner 30, respectively. A tuning voltage automatic up and down circuit, characterized in that.