KR850001307B1 - Automatic search level modulation circuit - Google Patents

Abstract

A modulation circuit stores tunable broadcasting frequencies into flip-flop memory device by scanning all frequencies at the time the power is switched on, allowing the corresponding frequency to be chosen automatically regardless of radio-field intensity. It consists of a first pulse generator (10), a power supply (B6), a flip-flop memory circuit (60), a second pulse generator (20), a positive edge detector (30), a delay circuit (40) and level converters (70)(80).

Description

Automatic search level conversion circuit

1 is an automatic search level conversion circuit according to the present invention.

FIG. 2 is a waveform diagram of each part of the circuit diagram shown in FIG.

* Explanation of symbols for main parts of the drawings

10: first pulse generator circuit 20: second pulse generator circuit

30: positive edge detection circuit 40: delay circuit

50: switch circuit 60: flip-flop portion

70,80: level conversion circuit

The present invention relates to an automatic search level conversion circuit that enables to tune a certain number of broadcasts regardless of the electric field strength.

In the prior art, auto-tuning relations differ from region to region, which is a problem in the region.

In the case of product makers, it was also difficult to select either Seoul or the province. Specifically, when the PLL synthesizer tuner tries to tune in automatically, there is an area where the electric field strength is different in each product maker, and there is an area where one station cannot be tuned. Too many areas were selected.

In view of the above-mentioned drawbacks of the prior art, the present invention scans the entire frequency at the same time as the power supply to store the number of tunes that can be tuned in 8 flip-flops, and automatically converts the tuning levels according to the stored numbers. It is invented to be able to.

Therefore, according to the present invention, a certain number of broadcasts can be tuned regardless of electric field strength in any region. In particular, it is necessary to fix the level for automatic tuning in the integrated circuit tuner and the circuit with the built-in automatic tuning, so it is possible to automatically tune according to Seoul, province, province, and province where there is a huge difference in electric field strength. In some cases, the application of the present invention to audio equipment, television, and communication equipment has a great effect.

Hereinafter, the present invention will be described in detail by the accompanying drawings.

)와, 플립플롭(F/F₈)의 출력단자(Q)와 플립플롭(F/F₉)의 출력단자(Q)를 앤드게이트(G₅) 및 저항(R₆,R₇) 트랜지스터(TR₃)로 구성된 레벨변환회로(70)와, 앤드게이트(G₆) 및 저항(R₈,R₉), 트랜지스터(TR₄)로 구성된 레벨 변환회로(80)를 각각 통하여 신호 레벨구동회로(B₅)의 입력측에 공통 접속하고, 또한 스위치(SW₃) 및 저항(R₁₀)으로 구성된 수동식 조작부(B₇)를 상기 신호 레벨 구동회로(B₅)의 입력측에 접속하여 구성한 것으로 도면의 설명중 미설명부호 B₃는 공지의 AM IF 및 검파회로이고, B₄는 공지의 FM IF 및 검파회로로서, 그 AM IF 및 검파회로(B₃)와 FM IF 및 검파회로(B₄)의 출력신호는 가변저항(VR₁) 및 다이오드(D₇)와, 가변저항(VR₂) 및 다이오드(D₈) 를 각각 통하여 신호 레벨 구동회로(B₅)에 인가되게 되어 있다.In the automatic search level conversion circuit of the present invention, as shown in FIG. 1, the first pulse generation circuit 10 composed of a resistor R ₅ , a capacitor C ₄ , and an inverter G _{4 is} provided with an AM / FM. It is connected to the output side of the power supply circuit B _{6 which also} serves as a switching switch, and the output side of the first pulse generating circuit 10 is flip-flop F / F ₁ -F / F ₈ through the diode D ₆ . Second pulse generating circuit composed of diode (D ₅ ), flip-flop (F / F ₉ ), resistor (R ₄ ), and capacitor (C ₃ ) at the same time as common connection to reset terminal of configured flip-flop unit 60 Via 20 is connected to the control terminal side of the analog switch SW ₂ connected to the detection circuit B ₁ of the known FM / AM signal, and is further connected to the output side of the first pulse generator circuit 10. Positive edge detection circuit composed of capacitor (C ₂ ) and resistor (R ₂ , R ₃ ), diode (D ₃ , D ₄ ), transistor (TR ₂ ), inverter (G ₃ ) on the output side of analog switch (SW ₂ ) 30, inverter G ₁ , G ₂ ) and a time delay circuit 40 composed of a resistor R ₁ , a capacitor C ₁ , and a diode D ₁ , respectively, connected to a known FM / AM synthesizer PLL circuit B ₂ . The common side is connected to the base of the transistor TR ₁ of the switch circuit 50 and the output side of the analog switch SW ₂ is connected to the flip-flop F / F ₁ -F / F ⁸ of the flip-flop unit 60. Commonly connected to the clock terminal, the output terminal Q of the flip-flop F / F ₄ of the flip-flop unit 60 and the output of the flip-flop F / F ₉ of the second pulse generating circuit 30 are connected. Terminals(

), And the output terminal Q of the flip-flop F / F ₈ and the output terminal Q of the flip-flop F / F ₉ are connected to the AND gate G ₅ and the resistors R ₆ and R ₇ . The signal level driving circuit 70 through the level converting circuit 70 composed of TR ₃ , and the level converting circuit 80 composed of the AND gate G ₆ , the resistors R ₈ , R ₉ , and the transistor TR ₄ , respectively. B ₅ ) is connected to the input side of the input side, and a manual operation unit B ₇ composed of a switch SW ₃ and a resistor R ₁₀ is connected to the input side of the signal level driving circuit B ₅ . Unexplained symbol B ₃ is a known AM IF and detection circuit, B ₄ is a known FM IF and detection circuit, and the outputs of the AM IF and detection circuit (B ₃ ) and FM IF and detection circuit (B ₄ ). The signal is applied to the signal level driving circuit B ₅ via the variable resistor VR ₁ and the diode D ₇ , and the variable resistor VR ₂ and the diode D ₈ , respectively.

If described in detail the effects of the present invention configured as described above.

When the power switch SW ₁ is connected, the power is supplied to the first pulse generating circuit 10 through the power circuit B ₆ which also serves as a known AM / FM switching switch, and the capacitor C _{4 of} FIG. As shown in a), the output terminal of the inverter G ₄ on the output side thereof is charged as shown in (b) of FIG. 2 until the charging voltage of the capacitor C ₄ reaches a constant voltage Vth. The pulse signal as shown is output. The pulse signal resets the flip-flop F / F ₁ F / F ₈ of the flip-flop unit 60 through the diode D ₆ , and the pulse signal is a diode of the second pulse generation circuit 20. Since flip-flop F / F ₉ is set through (D ₅ ), a high-potential signal is output to its output terminal Q as shown in (d) of FIG. 2, and low to its output terminal Q. The potential signal is output. At this time, because the flip-flop (F / F ₉₎ an output terminal (Q) of the high potential signal is a resistance (R ₄₎ a through condenser (C ₃₎ an after resetting the flip-flop (F / F ₉₎ filled in the output from the The output terminal Q of the flip-flop F / F ₉ has a high potential during the settling time t ₁ -t _{19 of the} resistor R ₄ and the capacitor C ₃ as shown in (d) of FIG. Will output a signal. As such, the high potential signal output from the output terminal Q of the flip-flop F / F ₉ conducts the analog switch SW ₂ .

In addition, since the pulse signal output from the first pulse generator circuit 10 is applied to the base of the transistor TR ₂ through the capacitor C ₂ and the resistor R ₃ of the positive edge detection circuit 30, the transistor (TR ₂ ) is turned on after the capacitor C ₂ is charged over a predetermined voltage (t _{2 in} FIG. ₂ ), and a low potential signal is outputted to the collector thereof, and this low potential signal is high potential in the inverter G ₃ . After being inverted into a signal, a pulse signal, which is a high potential signal, is output through the diode D ₃ as shown in (c) of FIG. 2, and this high potential signal is used to turn the transistor TR ₁ of the switch circuit 50. By conducting, the known FM / AM synthesizer PLL circuit B ₂ starts the "up" operation of the frequency.

In this state, when the broadcast is tuned at the time t ₃ as shown in (e) of FIG. ₂ , the signal level is known in the known AM IF and detector circuit B ₃ or FM IF and detector circuit B ₄ . After the signal is output, through the variable resistor (VR ₁ ) and diode (D ₇ ) or through the variable resistor (VR ₂ ) and diode (D ₈ ) and again through the known signal level drive circuit (B ₅ ) FM / AM signal Since it is applied to the detection circuit B ₁ , a high potential signal is output to the output side thereof. This high potential signal is applied to the broadcast channel selection terminal SD of the FM / AM synthesizer PLL circuit B ₂ to temporarily stop the "up" operation of the frequency currently being counted. In addition, the high potential signal output from the FM / AM signal detection circuit B ₁ is a clock terminal of the flip-flops F / F ₁ -F / F ₈ of the flip-flop unit 60 through the analog switch SW ₂ . However, since the high potential signal B ⁺ is applied only to the input terminal D of the flip-flop F / F ₁ , the high potential signal is output only to the output terminal Q thereof so that the flip-flop F / F ₁ is applied. It is applied to the input terminal D of F ₂ ).

Also, the high potential signal through the analog switch (SW ₂₎ is a delay circuit 40 to the drive (G ₁₎ at the discharge since the inversion of a low potential signal through the capacitor (C ₁₎ the charge voltage the resistance (R ₁₎ of the Therefore, when the charging voltage of the capacitor C ₁ is discharged below a predetermined voltage (t _{4 in} FIG. ₂ ), a low potential signal is applied to the input terminal of the inverter G ₂ so that a high potential signal is applied to the output side thereof. This high potential signal is output as shown in FIG. 2C through the diode D ₁ to turn on the transistor TR ₁ of the switch circuit 50, thereby providing an FM / AM synthesizer PLL circuit. (B ₂ ) again performs the "up" operation of the frequency.

In this state, if the broadcast is tuned again at the time t ₅ as shown in (e) of FIG. 2, the high potential signal is output from the FM / AM signal detection circuit B _{1 in the} same manner as described above. The / AM synthesizer PLL circuit (B ₂ ) stops the frequency "up" operation currently being counted, and the flip-flop (F / F ₂ ) is applied with a high potential signal to the input terminal (D). The high potential signal is output to the output terminals Q and Q of F / F ₁ , F / F ₂ , and after the delay of the delay circuit 40 is turned on, the switch circuit 50 becomes conductive again. The AM synthesizer PLL circuit B ₂ again performs an "up" operation of the frequency.

Hereinafter, as shown in (e) of FIG. 2, even when a broadcast is tuned at a time t ₇ , t ₉ , t ₁₁ , t ₁₂ , t ₁₅ , t ₁₇ , the same operation is performed as described above. The high potential signal is output from the flip-flops F / F ₁ -F / F ₈ of the flip-flop unit 60 corresponding to. In this state, as described above, when the charging of the capacitor C ₃ of the second pulse generating circuit 20 is completed and the flip-flop F / F ₉ is reset (t _{19 in} FIG. 2), its output A low potential signal is output to the terminal Q, the analog switch SW ₂ is opened, and a high potential signal is output to the output terminal Q thereof, and the AND gates G of the level conversion circuits 70 and 80 are output. ₅ ), (G ₆ ) is applied to one input terminal.

Accordingly, the output signals of the AND gates G ₅ and G ₆ are output from the flip-flops F / F ₁ -F / F ₈ of the flip-flop unit 60 in accordance with the number of broadcasting stations as described above. Determined by

That is, when the broadcast is tuned to less than four stations, the high potential signal is output only to the output terminals Q of the flip-flops F / F ₁ -F / F ₃ and the flip-flops F / F ₄ -F / F ₈ Since the low potential signal is output to the output terminal Q of the low potential signal, the low potential signal is output to the output terminals of the AND gates G ₅ and G _6. Accordingly, the transistors of the level conversion circuits 70 and 80 are output. Since (TR ₃ ) and (TR ₄ ) are off, the level signals output from the known AM IF and detection circuits B ₃ and FM IF and detection circuits B ₄ are applied to the signal level driving circuits B ₅ as they are. do.

However, when the broadcast is tuned to less than eight stations in four or more stations, since the low potential signal is output from the output terminal Q of the flip-flop F / F ₈ , the level conversion circuit 80 does not operate as described above. At this time, since the high potential signal is output to the output terminal Q of the flip-flop F / F ₄ , the high potential signal is output to the output terminal of the AND gate G ₅ , and the transistor TR ₃ is output by the high potential signal. Is conducted, a portion of the signal output from the AM IF and detection circuit B ₃ and the FM IF and detection circuit B ₄ and input to the signal level driving circuit B ₅ is applied to the resistor R _{6 as} described above. Flows through the transistor TR ₃ , and accordingly, a signal attenuated by the signal flowing through the resistor R ₆ is applied to the known FM / AM signal detection circuit B ₁ through the signal level driving circuit B ₅ . The search level is automatically controlled.

In addition, when the broadcast is tuned to eight or more stations, since the high potential signal is output from all the output terminals Q of the flip-flops F / F ₁ -F / F ₈ of the flip-flop unit 60, the level converting circuit 70 The transistors TR ₃ and TR _{4 of} ) and 80 are turned on so that a part of the signal input to the signal level driving circuit B ₅ as described above is resistors R ₆ and R ₈ . After being distributed through and attenuated more, the search level is automatically controlled since it is applied to the FM / AM signal detection circuit B ₁ .

In addition, when the switch SW ₃ is connected to the on terminal in order to control the search level manually, part of the signal applied to the signal level driving circuit R ₅ is the switch SW ₃ and the resistor R ₁₀ . Since it is distributed through, it is possible to control the search level by connecting the switch (SW ₃ ) from the exterior of the product.

As described above, the present invention can tune to a certain number of broadcasts in any region regardless of electric field strength, and in particular, the level within which a product can be automatically tuned in a circuit in which a synthesizer tuner and an automatic tuner are built in the conventional product is provided. In addition, there are some places where Seoul and the province, where there is a lot of difference in electric field strength, and there are some places where they are almost impossible to use, but the present invention can be applied to audio equipment, TV, and communication equipment. In this case, there is a profound effect that can eliminate the above drawbacks.

Claims (4)

The output side of the first pulse generating circuit 10 including the resistor R ₅ , the capacitor C ₄ , and the inverter G ₄ is connected to the flip-flop F / F of the flop-flop unit 60 through the diode D ₆ . Second pulse generation circuit 20 commonly connected to the reset terminal F ₁ -F / F ₈ and composed of diode (D ₅ ), flip-flop (F / F ₉ ), resistor (R ₄ ), and capacitor (C ₃ ) ) Is connected to the control terminal side of the analog switch SW ₂ connected to the known FM / AM signal detection circuit B ₁ , and its output side is connected to the flip-flop F / F ₁ -F / F ₈ . In addition to the common connection to the clock terminal, the output side of the analog switch (SW ₂ ) and the output side of the first pulse generator circuit 10 is connected to the inverter (G ₁ , G ₂ ), resistor (R ₁ ), capacitor (C ₁ ) , Time delay circuit 40 composed of diode (D ₁ ), capacitor (C ₂ ) and diode (D ₃ , D ₄ ), resistor (R ₂ , R ₃ ), transistor (TR ₂ ), inverter (G ₃ ) Known FM / AM through positive edge detection circuit 30 composed of The output terminal Q of the flip-flop F / F ₉ of the second pulse generation circuit 20 is connected to the driving switch circuit 50 of the general-purpose PLL circuit B ₂ , and the gate gate G is connected to the driving switch circuit 50. ₅ ), one side input of the level conversion circuits 70 and 80 composed of (G ₆ ) and resistors (R ₆ , R ₇ ), (R ₈ , R ₉ ) transistors (TR ₃ ), (TR ₄ ), respectively In addition to the common connection to the terminals, the output terminals (Q) and (Q) of the flip-flops (F / F ₄ ) and (F / F ₈ ) are respectively connected to the other input terminals thereof, and then the output side thereof has a known signal level. An automatic search level converting circuit comprising a common connection to an input side of a driving circuit (B ₅ ). delete delete The automatic search level change according to claim 1, wherein a manual operation unit (B ₇ ) composed of a switch (SW ₃ ) and a resistor (R ₁₀ ) is connected to an input side of a known signal level driving circuit (B ₅ ). To return.

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