KR910007631Y1 - Analog data monitoring circuit for cpu - Google Patents

Abstract

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Description

CPIU's Analog Data Sensing Circuit

1 is a conventional CPI analog output circuit diagram.

2 is an analog data detection circuit diagram of the present invention CPI.

3 is a waveform diagram of each part of (a) to (i) in FIG.

* Explanation of symbols for main parts of the drawings

1, 2: Latch buffer 3: Operation processing unit

4, 10, 11: Comparator 5: Selector

6: D / A Converter 7: Switch

8: Databus 9: Address Cover

12: address selector 13: buffer

AND1, AND2: AND gate

The present invention relates to an analog output circuit of an automatic control system, and more particularly to an analog data detection circuit of CPI to detect the data of the CPU (CPU) to eliminate the error state of the analog data output.

In general, the automatic control system sets analog values through a program set in CPI to control external conditions of the control equipment such as air, temperature and pressure.

In the conventional analog output circuit, as shown in FIG. 1, when the system clock CK is supplied to the latch buffer 1, the data Dn from the data bus 8 is latched through the latch buffer 1; After that, it is transmitted to the input terminal A of the selector 5 and the input terminal B of the arithmetic processing unit 3, and is latched through the latch buffer 2 to latch the data Dn-1, and the data Dn-1 thereof. Is transmitted to the input terminal B of the selector 5 and the input terminal A of the arithmetic processing unit 3.

At this time, the arithmetic processing unit 3 processes the data Dn (Dn-1) transmitted from the latch buffers 1 and 2 and applies the data Q to the comparator 4 as a data Q. Compare with the set data (P). In this case, when the operation data Q is smaller than the set data P, a low potential is generated from the comparator 4 so that the selector 5 controls the selector 5, and then the data Dn of the latch buffer 1 is selected. The analog (D) / analog (A) converter 6 outputs the analog data. At this time, the output of the comparator 4, which has a low potential, becomes a low potential through the Ant gate AND1, and clocks the latch buffer 2. Since it is impossible to supply, (Dn-1) of the latch buffer 2 does not change.

However, in the abnormal case in which the operation data Q is larger than the set data P in the comparator 4, the high potential is generated from the comparator 4 and the selector 5 is controlled to control the data of the latch buffer 2. After Dn-1) is selected, it is output as analog data through D / A converter (6). At this time, the output of high-potential comparator (4) is clocked to latch buffer (2) through AND gate (AND1) with system clock. As it is supplied to, it latches the next data.

Therefore, if the latest data (Dn) output from CPI is compared with the previous data (Dn-1) and is similar to the previous data (Dn-1), the latest data (Dn) is output and the previous data (Dn-1) In case of abnormality that is suddenly large, the previous data Dn-1 is output.

However, in the conventional analog output circuit as described above, the computer outputs data Dn, but when the actual drive data Dn-1 is output, the CPI does not detect such a condition and causes a malfunction. There was this.

The present invention, in view of the conventional defects such as analog output data to the CAPI oil to prevent the malfunction of the system by abnormal data to devise an analog data detection circuit of CPI, which will be described in detail by the accompanying drawings As follows.

2 is an analog data sensing circuit diagram of the present invention CPI. As shown therein, the output data of the latch buffer 1 that receives the data of the data bus 8 in response to the supply of the system clock CK is selected by the selector 5. The output data of the latch buffer 2, which is applied to the input terminal A of the input terminal B and the input terminal B of the arithmetic processing unit 3, and receives the output data of the latch buffer 1, is the terminal B of the selector 5. ) Is applied to the terminal A of the calculation processing section 3, and is arithmetic processing, and is applied to the comparator 4 of the output data 2 of the calculation processing section 3 to set data P of the switch 7 and The output of the comparator 4 is clocked to the latch buffer 2 through the AND gate AND1 together with the system clock CK, and controls the selector 5 and the terminal A. In CPI's analog output circuit configured to output data through the A / D converter 6 after selecting data from (B), After the data of the latch buffers (1) and (2) are applied to the input terminals (B) of the comparators (11) and (10), respectively, the output data of the selector (5) is supplied by the clock supply by the output of the comparator (4). To be compared, the interrupt signal INT is applied to the CPI via the AND gate AND2, the address selector 12 is controlled to select an address of the address bus 9, and the buffer 13 is controlled to The output data of the selector 5 is transmitted to the data bus 8.

Here, the comparator 10 is set when the input data is the same, and the comparator 11 is configured to be set when the input data is different.

(A) to (i) in FIG. 3 are waveform diagrams of each part of the drawing, (a) is a system clock (CK) waveform, (b) (c) is data of the latch buffer (1) and (2), and (d) is The output waveform of the comparator 4, (e) is the output data of the selector 5, (f) (g) is the output waveform of the comparator 10 (11), (h) is the interrupt signal (INT), (i ) Shows the detection data of CPI.

Referring to the effect of the present invention configured as described above are as follows.

First, as described in the prior art, the data as shown in FIG. 3 (b) (c) through the latch buffer 1 ((1)) in accordance with the supply of the system clock 0 as shown in FIG. Dn-4) (Dn-3) (Dn-2) (Dn-1) are sequentially transmitted, and the output of the comparator 4 as shown in FIG. 3 (d) controls the selector 5 The data Dn-4 and Dn-2 as shown in FIG. 5E are output.

Here, as shown in FIG. 3 (b) (c), the latest data Dn-3, which is the output of the latch buffer 1, is larger than the previous data Dn-4, which is the output of the latch buffer 2, as shown in FIG. In the case of the output, the output of the comparator 4 becomes high potential as shown in FIG. 3 (d), and then controls the selector 5 and then transfers the previous data Dn as shown in FIG. -4) is selected and output via the D / A converter 6.

At the same time, the output data Dn-4 and Dn-3 of the latch buffers 1 and 2 are supplied to the comparators 10 and 11 with the output of the comparator 4 having the high potential pulse. After being applied to the comparators 11 and 10, the output data Dn-4 of the selector 5 as shown in FIG. 3 (e) becomes the same, as shown in FIG. 3 (f). The comparator 10 outputs a high potential and the comparator 11 outputs a high potential as shown in FIG. 3 (g) because the input data Dn-4 and Dn-3 are different. The output of (11) outputs a high potential pulse as shown in FIG. 3 (h) through the AND gate AND2, and its pulse is applied to the CPI as an interrupt signal and clocked to the address selector 12. As the address supplied and passed through the address bus 9 drives the buffer 13, the output data Dn-4 of the selector 5 as shown in FIG. 3 (j) passes through the buffer 13. Authorization to the data bus (8) By doing this, the output value of the address designated by the computer is read correctly.

In addition, as shown in FIG. 3 (b) (c), when the latest data Dn-2, which is the output of the latch buffer 1, is similar to the previous data Dn-4, which is the output of the latch lever 2, as shown in FIG. As shown in Fig. 3 (d), the output of the comparator 4 becomes low potential and then controls the selector 5 so as to show the latest data Dn-2 as shown in Fig. 3 (e). Is selected and output.

At the same time, as the output of the comparator 4, which is at a low potential, stops the clock supply of the comparators 10 and 11, the driving of the comparators 10 and 11 is stopped so that the output data Dn-2 of the selector 5 is stopped. Is output through the D / A converter 6.

Thereafter, as shown in FIG. 3 (b) and (c), the latest data Dn-1, which is the output of the latch buffer 1, is output and transmitted to the CPI via the data bus 8.

Therefore, the computer accurately loses the output value of the designated address, and in the next step, the CPI sees the output value first and then outputs the next output correctly.

As described in detail above, the present invention not only performs an accurate calculation and is detected by CPI through an interrupt function when an analog data is outputted, but also an analog output can be newly applied to protect the driver of the system. There is an effect that can improve the reliability of.

Claims (1)

The output data of the latch buffer 1 accommodating the data of the data bus 8 and the latch buffer 2 accommodating the data of the latch buffer 1 are computed and compared with the set values through the comparator 4. The output of the comparator 4 controls the selector 5 so that the output data of the latch buffers 1 and 2 is applied to each of the comparators 11 and 10 and then to the output of the comparator 4. The clock is supplied to the output data of the selector 5, the interrupt signal INT is applied to the CPI through the AND gate AND2, and the address selector 12 is controlled to control the address bus 9. The CPI analog data sensing circuit is configured to select an address and control the buffer (13) to transmit the output data of the selector (5) to the data bus (8).