KR910007532B1 - Multilayer resist structure device and manufacturing method - Google Patents

Abstract

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Description

[Name of invention]

Component having multi-layer resist structure and manufacturing method thereof

[Brief Description of Drawings]

1 is a side cross-sectional view of the resist structure of the present invention.

2 is a side cross-sectional view showing the structure of the resist layer in each step, and a flowchart of steps of preparing and using the resist structure of the present invention to generate rise and fall regions on a substrate.

Detailed description of the invention

[Background of invention]

FIELD OF THE INVENTION The present invention relates to the field of microelectronics, and more particularly to resist structures used to fabricate circuit devices.

An integrated circuit is an electronic device in which a significant number of each microelectronic device of very small size is located on the bottom of the device or prepared on a single support surface called a chip supporting the device. Microelectronic devices are formed of layers of semiconductor, insulator and conductor materials selected and arranged to have specific electronic properties. Each microelectronic device is typically very small, with lateral dimensions less than a few micrometers and smaller in thickness. Thousands of devices can be formed on a single chip with a lateral size of several centimeters and weighs less than one gram and can be connected together in a logic array to form complex electronic circuits that can require hundreds of times the area and weight of an integrated circuit. Can be. The development of the microelectronics sector is based on many improvements made in the electronics sector for consumer, business and military use.

When each microelectronic device is so small that it cannot be seen with the naked eye, it is quite difficult to manufacture it on a large scale. Because these microelectronic devices are each very small and the number of devices on the chip is very large, these devices cannot be manufactured by conventional techniques such as cutting, bonding, welding and soldering. Recently, various new technologies have been used to manufacture this device, one of which is the subject of the present invention, microlithography.

In lithography applied in the manufacture of microelectronic devices, the pattern is disposed on the surface of the chip or on a layer of a particular material deposited on the chip. The pattern can then be filled with another material, or part of the pattern can be removed by etching. Different patterns are then disposed on the surface of the final structure and on other materials deposited within the pattern. This process of panning the surface and then depositing or removing the material can be repeated many times to form a complex pattern of layers of different materials and geometries. The final structure may include thousands of microelectronic devices placed side by side on a chip. If the materials and geometries are properly selected and all individual manufacturing steps are performed correctly, the final integrated circuit exhibits desirable electronic properties.

Lithography is particularly suitable for making very small microelectronic devices because it includes photographic techniques such as optical size reduction, image exposure, and image development. Specifically, the desired pattern of one layer in the manufacturing process is readily prepared and prepared in a template of large size that is visible. The pattern of the template is then projected onto the surface of the chip using projection light, such as visible light, electron beam, or ion beam. Prior to projection, the surface of the chip is covered with a resist structure that is a layer or layer array of materials sensitive to exposure by projection illumination. The resist structure is then developed by photographic shaping techniques to reproduce the exact geometry of the pattern of the template on the surface, except that the size of the pattern is reduced to hundreds or thousands of times.

The resist structure must be readily used for large scale manufacturing operations, be reproducible, and be fairly precise in faithfully reproducing the template geometry on the chip. In the most basic method, a single layer of resist material is deposited on the surface of the chip and then exposed and developed. The surface of the chip in the middle of the manufacturing process is not intentionally smooth. That is, microelectronic devices are typically combined with shapes such as raised areas called mesas or falling areas called vias. If a layer of resist material of uniform thickness is placed on this surface, the top surface of the resist layer becomes irregular along the form of mesas or vias. This irregularity is undesirable because the image of the template cannot be precisely focused on an irregular surface.

In order to eliminate the problem of irregular top surfaces on the resist material, it is known to use a fairly thick polymer layer called a planarizing layer deposited over mesas and vias. The planarization layer is so thick and provided in this way that it fills the area between mesas and vias, and has a planar top surface so that an image of the template can be focused on this surface. If a planarization layer is used, at least one layer must be deposited over the planarization layer so that it can selectively define and remove the resist area when preparing to form an incidental shape.

One of these methods uses three layers: a planarization layer deposited on the chip, a separate thin image layer to which the pattern of the template is first exposed, and a separation layer between the two layers. Illumination radiation exposes the pattern of the template onto the surface of the image layer, and the exposed pattern is developed. This pattern is transferred to a separation layer of durable material that protects the portion of the planner layer that is not removed in the next step of transferring the pattern of the separation layer to the planarization layer. These three layers of resist structure are useful in many manufacturing processes.

However, recently used three layer resist structure methods have certain serious drawbacks resulting from the inability of separation layer materials to have desirable bonding properties. In certain manufacturing methods, it is preferable to illuminate different templates and different parts of the same template with different illumination radiation. The already known separation layer materials cannot be readily used for different forms of illumination radiation and also do not have the resistance of etching necessary to protect the non-patterned portions of the planarization layer while etching the patterned portions. The utility of monolithic resist structures useful for light and electron beam illumination becomes desirable from a manufacturing standpoint. This single type of resist structure allows the use of two patterning methods with a single separation layer material, since different patterning methods can be used on a single layer.

Accordingly, there is a need for an improved three-layer resist structure in which the material of the separation layer is selected to protect the planarization layer during etching and is also compatible with the use of light and electron beam illumination. The present invention satisfies this need and also provides related advantages.

[Summary of invention]

The present invention provides a resist structure used to pattern a substrate when making a microelectronic device. The resist structure is combined with a separation layer that is compatible with the use of light beams and electron beam illumination. Since the material of the separation layer transmits visible light, the illumination pattern can be easily aligned with the current shape of the surface to precisely match the current shape and the shape to be added. Since the separation layer prevents etching during pattern transfer to the planarization layer, the pattern can be easily exposed on the image layer, transferred to the separation layer, and transferred to the planarization layer.

According to the present invention, a component having a multi-layer resist structure on a substrate includes a substrate, a planarization layer of a polymer material overlying the substrate, a separation layer of translucent and conductive material overlying the planarization layer, and the separation thereof It consists of an image layer of resist material overlying the layer. As a light transmitting and conductive material, a mixture of indium oxide and tin oxide called indium tin oxide is preferable. Indium tin oxide is known as a conductive material but has not been used as a separation material in multilayer resist structures.

Also in accordance with the present invention, a method of providing a component having a multilayer resist structure etched on a substrate finishes the substrate, deposits a planarization layer of polymeric material overlying the substrate, and tops the cranerization layer. Depositing a separation layer of transmissive and conductive material overlying, depositing an image layer of resist material overlying the separation layer, forming and developing a pattern in the image layer, transferring the pattern to the separation layer, and a planarization layer Delivering the pattern. The separation layer is preferably made of indium tin oxide.

The planarization layer is made of a material that can easily be provided on an uneven surface, such as a substrate having mesas or vias, but itself having a relatively flat planar top surface. Many standard polymeric materials can be used. Most are applied into the solution together with the solvent by flowing a solution of the polymer material onto the substrate surface, spinning off the excess solution, and drying the remaining material.

The separation layer is made of a light transmissive and conductive material, preferably indium tin oxide. The term indium tin oxide refers to a mixture of indium oxide and tin oxide. Indium tin oxide may be regarded as indium oxide doped with tin or indium doped tin oxide, respectively, when indium oxide or tin oxide predominates. Although a mixture of about 91% indium oxide and 9% tin oxide is permeable and electrically conductive, this material has not been used as a separation material in the resist structure. The present invention is not limited to this particular compound of indium tin oxide, although no limitations to the compound that can be implemented in this system are known. Translucent and conductive materials, preferably indium tin oxide, may be provided to the substrate in any satisfactory manner, preferably reactive sputtering.

The use of a light transmissive material allows the surface of the substrate to be visually seen through the separation layer, which has the major advantage that the pattern of the template is precisely aligned with the current structure on the substrate using a commercially available optical alignment device. The use of a conductive material has the advantage that the separation layer can be used to form an electron beam pattern in the image layer. When the electron beam is used to pattern the image layer, the lower isolation layer must be electrically conductive to complete the circuit with the electron gun, but static on the surface of the image layer to deflect the electron beam and distort the pattern. An electric charge will be generated. Translucent and conductive materials which have been satisfactory for use with resist structures to provide these advantages have not been previously known.

The material of the separation layer should also prevent etching by the good techniques used to transfer the pattern to the planarization layer. A preferred technique is the reactive ion etching technique, which is a dry etching technique that produces a transfer pattern with a vertical wall that is directional and does not exhibit the underlying transfer characteristics of the wet chemical transfer process.

The image layer is made of a resist material that can be exposed and developed to produce a pattern corresponding to the reduced pattern of the template on the upper surface of the resist structure. The image layer is usually provided very thin, about 0.2 micrometers thick, to allow high resolution of the image. The image layer can be positive or negative resist. Many light and electron beam resist materials are known and commercially available.

It will be appreciated that the present invention provides improvements in the field of resist structures for use in making microelectronic devices. The light transmissive and conductive separating layer allows for precise optical alignment of the pattern and the substrate and can be used for light and electron beam illumination radiation. The material is sufficiently resistant to etching by conventional dry etching techniques, allowing sharply formed patterns to be transferred to the lower planarization layer. Other features and advantages of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate by way of example the principles of the invention.

Detailed Description of the Preferred Embodiments

The present invention is implemented with a multilayer resist structure 10 on a substrate 12 as shown in FIG. As used in this figure, the substrate 12 is a piece in which the multilayer resist structure 10 is deposited and used together. The substrate 12 may be the base with nothing deposited. Optionally, as shown in FIG. 1, the substrate 12 includes a portion of the device structure already deposited on the base 14 together with the base 14. In FIG. 1, the silicon layer 16 is previously deposited on the base 14 and etched to form a raised region 18 therein, although the invention is not limited to using any particular structure previously deposited. Do not. One of the advantages of this method is that it is compatible with a wide variety of bottom substrates 12.

The resist structure 10 includes a planarization layer 20 overlying the substrate 12. The planarization layer 20 is of sufficient thickness to fill the valleys 22 between the raised regions 18. The top surface of the planarization layer 20 is relatively flat and acts as a support for the top layer. The planarization layer 20 may be of any polymeric material that may be provided to fill in the valleys and has a flat top surface 24. Preferably, the plannerization layer is made of a polymer such as polymethylmethacrylate (PMMA) that is a resist material and can be dissolved in an organic solvent. The solution of PMMA flows out onto the substrate 12 and excess solution is removed by spinning the substrate. During outflow, the solution diffuses to cover the surface of the substrate 12 and fills the valley 22. The substrate covered with the solution is then dried to leave a flat top surface 24 suitable for other processes. The maximum thickness of the craniation layer is typically about 2 micrometers. Optionally, the planarization layer can be baked to further cure.

Separation layer 26 overlies the planarization layer 20. The separation layer 26 is made of a light transmissive and conductive glass material, preferably indium tin oxide, most preferably a compound of 91 atomic% indium oxide and 9 atomic% tin oxide. Indium tin oxide is electrically conductive and transmits visible light. Good composites of 91 atomic percent indium oxide and 9 atomic percent tin oxide have sufficient conductivity and light transmission to enable them to operate as a separation layer.

Separation layers are provided in any prior art. For example, an indium tin oxide layer is deposited on the nonmetallic planarization layer 20 to a thickness of about 0.1 to 0.2 micrometers by sputtering of a compound target in a conventional manner.

Conventional prior art separation layers are sometimes formed of metals such as aluminum, rhodium, or silicon that are conductive but do not transmit visible light. While these materials provide acceptable results in certain operations, attempts to align the projected image of the template on the substrate 12 in precisely accurate positions have been uncertain. Optionally, the separation layer is sometimes formed of silicon dioxide or other nonconductive oxides. When the thickness is sufficient to thin the resist by reactive ion etching, the silicon dioxide becomes translucent. However, this is not a conductor and cannot be used with the electron beam lithography form of the etching pattern. Silicon dioxide is further limited in use as it is attacked by fluorine which can be released from the polymer used to cover the electrode during dry etching. The separation layer material of the present invention eliminates these problems and generates the advantages described above.

The image layer 28 is disposed on the separation layer 26. Since the pattern of the template is exposed and developed into this image layer 28, the image layer is selected to be a resist material sensitive to the illumination radiation to be used. The resist material is structurally changed when exposed to illumination radiation and can then be developed in the developing solution to remove or maintain the exposed area. When the exposed area is removed, the resist material is called positive resist. When the exposed area is maintained, the resist material is called negative resist. Examples of resist materials suitable for use as the imaging layer 28 include Shipley Micropoitive or American Hoechst AZ series and Kodak 809 (positive photoresist), Kodak 747 and Micro. Microneg (sub photoresist), PMMA (electron beam positive resist), and P4CS (electron beam sub resist). These resist materials are provided on top of the separation layer 26 in accordance with standard practice. For example, the solution is prepared with P4CS [poly-4-chlorostyrene] in MIBK [methylisobutylketone] and then spilled onto the surface. The excess solution is removed by spinning the substrate. The thickness of the P4CS resist layer remaining after drying to remove the solvent is typically about 0.2 to 0.5 micrometers.

In the use of the multilayer resist structure 10, the structure 10 is first deposited in the manner just described. Next, as shown in FIG. 2, the pattern in the image layer 28 is determined by projection illumination, typically beam or electron beam illumination. The material of the imaging layer 28 is selected as a resist for the illumination radiation to be used. The exposed image is then developed in the developing solution described for the selected resist material, so that the pattern 30 is etched through the image layer 28.

The pattern is preferably transferred to the separation layer by a dry etching technique such as argon sputter etching. The resist structure is disposed in an ionized argon atmosphere, and a negative voltage is applied to the resist structure. Argon ions are accelerated toward the part of the separation layer 26 exposed through the opening of the pattern 30 through the image layer 28. Argon ions remove the indium tin oxide exposed from the separation layer 26, so that the pattern 30 is transferred to the separation layer.

The pattern is preferably transferred to the planarization layer 20 by oxygen reactive ion etching. This technique has the advantage of being highly directional and generates a straight sided pattern downward in the planarization layer 20. The resist structure is disposed in an oxygen atmosphere that is excited by a radio frequency signal to generate positive oxygen ions. Since a negative plasma voltage is applied to the resist structure, oxygen ions are accelerated toward the portion of the planarization layer 20 that is exposed through the opening of the pattern 30. Oxygen ions remove material from the planarization layer 20 to transfer the pattern 30 to the planarization layer 20. Since the planarization layer 20 is relatively thick, reactive ion etching must continue for a period of time to fully etch the pattern 30 through the planarization layer. Reactive ion etching is powerful and quickly removes the remainder of the image layer 28. Therefore, the remaining non-patterned portion of separation layer 26 is highly resistant to reactive ion etching, so pattern 30 is faithfully transferred to planarization layer 20 without rounding the edges.

The pattern 30 is now fully transferred to the planarization layer 20 under the substrate 12. Pattern 30 is used for its intended purpose. 2 shows by way of example two different subsequent processes which are optional. In one process, the conductor layer 31 is fixed through the opening of the pattern 30 and thus lies on top of the substrate 12 only in the region of the opening. In another method, the material is removed from the raised portion 18 of the substrate 12 by etching through the openings in the pattern 30. After these operations are completed, the resist structure 10 is removed by dissolving the planarization layer 20. If necessary, the whole process is repeated with another new template and resist structure to provide another microelectronic circuit on the substrate 12.

The method of the present invention has been successfully used on test pieces having light and electron beam pattern shapes. Ray illumination is good for large structures that do not require high resolution of the structure. For example, light illumination can be used to define the elevation area or the mesa itself. Electron beam illumination can have higher resolution and can be used to define precise patterns such as submicrometer gate structures in field effect transistors. The separation layer of the present invention is useful for light beam and electron beam illumination by allowing alignment by virtual means. This resist structure and process was used to provide a submicron 8x8 multiplier large scale integrated (LSI) circuit with over 1400 polysilicon gate transistors.

The present invention provides an improved method for carrying out the lithography process in the manufacture of microelectronic devices. Translucent and conductive materials such as indium tin oxide, used as separation layers, provide good protection for the non-patterned portions of the planarization layer during reactive ion etching. Since it is transmitted at the required thickness, the pattern of the template can be precisely aligned and matched with the substrate. Conductive conduction of electron beam illumination is also done electrically, so electron beam pattern formation can be used.

While one particular embodiment of the invention has been described in detail for purposes of illustration, various modifications of the invention may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims (14)

A component having a multilayer resist structure on a substrate, the component comprising: a substrate, a planarization layer of polymer material overlying the substrate, a transmissive and conductive material overlying the planarization layer, and a resist overlying the separation layer Component consisting of an image layer of material. The component of claim 1, wherein the translucent and conductive material is indium tin oxide. The component of claim 1 wherein the planarization layer is about 2 micrometers thick. The component of claim 1, wherein the separation layer is about 0.1 micrometers thick. The component of claim 1, wherein the image layer is about 0.2 to 0.5 micrometers thick. A component having a multilayer resist structure on a substrate, the component comprising: a separation layer consisting essentially of a substrate, a planarization layer of a polymeric material overlying the substrate, a mixture of indium oxide and tin oxide overlying the planarization layer, and a separation layer And an image layer of resist material overlying the. A method of making a component having a multilayer resist structure etched on a substrate, the method comprising: finishing a substrate, depositing a planarized layer of polymeric material overlying the substrate, and translucent overlying the planarized layer And depositing a separation layer of a conductive material, depositing an image layer of a resist material overlying the separation layer, depositing an image layer of a resist material overlying the separation layer, and forming a pattern in the image layer. Developing, transferring the pattern to the separation layer, and transferring the pattern to the planarization layer. 8. The method of claim 7, wherein the translucent and conductive material is indium tin oxide. 8. The method of claim 7, wherein the planarization layer is about 2 micrometers thick. 8. The method of claim 7, wherein the separation layer is about 0.2 micrometers thick. 8. The method of claim 7, wherein the image layer is about 0.2 to 0.5 microns thick. 8. The method of claim 7, wherein transferring the pattern to the separation layer is performed by argon sputter etching. 8. The method of claim 7, wherein transferring the pattern to the planarization layer is performed by oxygen reactive ion etching. A component produced by the method of claim 7.

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