KR910007393B1 - Dual-port memory control signal generation circuit - Google Patents

Abstract

The circuit for providing the stable timings to the direct data transfer and memory writing, integrating the system into a single block, and removing the glitch and unknown conditions when accessing the memory separates the timing process to the one for the direct data process and another for the writing and refreshing of the memory. The circuit includes a counter (10) for supplying the signal converted by the grey coding method, a decoder (20) for generating strobo signal for row and column address, a dual port request signal generator (40) for generating the serial-output enable signal (DT), and a dual port memory (50).

Description

Dual Port Memory Control Signal Generation Circuit for Picture-in-Picture Controller

1 is a block diagram according to the present invention.

2 is a detailed circuit diagram of FIG. 1 according to the present invention.

3 is a state dimming diagram of the counter portion 10 of FIG. 2 according to the present invention.

4 is an operation timing diagram of FIG. 2 according to the present invention.

* Explanation of symbols for main parts of the drawings

10: counter section 20: status decode logic section

30: selector 40: dual port request signal generator

50: dual port memory 60: CALTI

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual port memory control circuit in a picture-in-picture controller (hereinafter, referred to as a " PIP ") controller. In particular, the present invention relates to a short read access timing in operation of a PIP. A stable memory read / write operation can be realized by separating the timing of direct data transfer, which is an essential operation, from the timing of normal operations of memory write and refresh, for a serial portlet operation that satisfies the requirement. It relates to a control signal generation circuit.

In general, a picture-in-picture controller is used to display certain other pictures as small size pictures on a single Cathod Ray Tube (CRT) screen. This means that a separate screen can be inserted into a screen of a small size in a different part of the currently displayed screen in addition to the currently displayed content. In order to perform the PIP, the image signal of the small screen for insertion is digitized and recorded in a memory, and when the display is read out in accordance with the synchronization signal of the currently displayed main screen, the small screen can be inserted into HanCTI to display a plurality of screens. have.

In the case of using a DRAM for image signal recording for a conventional PIP, a write operation for recording image data in a memory in a video memory access, and a read operation for reading out for display on a serial port, that is, the two operations It can't run asynchronously, either using a separate buffer from the DRAM, or abandoning either read / write operation, which doesn't provide stability. On the other hand, in the case of the PIP using the dual port memory, the memory write operation occurs simultaneously with the operation of direct data transfer (hereinafter referred to as "DT") for read. At this time, since the write operation is ignored and operated by DT, there is a problem in that a new value cannot be written to the memory.

Accordingly, an object of the present invention is to provide a circuit capable of stably providing timing and memory write timing for DT processing in order to effectively perform memory writing and DT operations in a page mode.

Another object of the present invention is to provide a circuit that can be modularized into a single block of the system and can separate all the newly generated data by writing the DT and the memory write timing.

It is still another object of the present invention to provide a circuit that can eliminate glitches and unknown states in a memory access operation.

According to an aspect of the present invention, there is provided a counter unit for generating a clutch-free signal by a method of inputting and counting a horizontal sync signal and a divided signal of a write clock by clicking and counting the gray sync code, and outputting the counter unit. The state decoding logic unit which decodes the state and latches it according to the clock signal and generates a memory access control signal, and writes data continuously input by the control signal of the state decoding logic unit to the memory in page mode and then takes an extra time. It is characterized by consisting of a selection unit for controlling the DT operation.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

및 기입신호

를 받으며 상기 듀얼포트요구발생부(40)의 출력단과 연결되어 직렬 출력 인에이블신호

를 받아 선택 제어 신호에 의해 상기 듀얼 포트 메모리 (50)에 입력하는 선택부(30)로 구성된다.1 is a block diagram according to an embodiment of the present invention, in which a counter is input latched on a clock input to an input terminal 11 and an output fed back based on a horizontal synchronization signal to repeat N-count counts in a gray code generation method. Connected to the output unit of the counter 10 and the output of the counter 10 to decode the output of the counter 10 to generate row and column address strobe signals according to normal and DT processing of the dual port memory 50. A state decoding logic unit 20 for stabilizing an output operation by latching according to the input clock signal of the input terminal 11 and for writing data to the dual port memory 50 to realize PIP in the CALTI 60. A dual port request signal generator 40 generating a serial output enable signal DT for reading and outputting a write signal WE and video data, and connected to an output terminal of the state decode logic 20. Column address strobe signal

And write signal

A serial output enable signal connected to the output terminal of the dual port request generator 40

Received by the selection control signal to the dual port memory 50 is composed of a selection unit 30.

Referring to the embodiment of the present invention according to the above configuration, the counting state is shifted by a reset by a signal divided by two and a horizontal synchronous signal divided by the write basic clock inputted to the input terminal 11 of the counter unit 10. A gray coded decimal counted signal is generated. When the output of the counter unit 10 is input to the state decoder logic unit 20, the signal generated by the counter unit 10 is decoded and the delayed values are equalized by latching the decoded values, resulting in glitch and instability. It stabilizes from the result and generates strobe signals of the row and column addresses of the dual port memory 50 for normal and DT processing. In this case, when the output of the state decoder logic unit 20 and the output of the dual port request generation unit 40 are multiplexed by the selector 30, the row and column address strobe signals required by the dual port memory 50 and The DT and write enable signals are generated so that the dual port memory 50 can be accessed stably. When the page mode is not written, DT processing and memory refresh functions are executed.

FIG. 2 is a detailed circuit diagram of the counter unit 10 and the state decoder logic unit 20 of FIG. 1 according to the present invention. U0 and U21 are flip-flops (D Type FFX2), U1-U17 are NAND gates, and U18 are Noah gate, U22-U23, and U26 are AND gates, U24, U25, and U27 are inverters, and the input terminal 11 corresponds to the clock input terminal 1 and the 1st, 2nd clear stages 2 and 3 stage. The clock input terminal 1 is connected to the clock terminal CK of the flip-flop U0, the first and second clear terminals 2 and 3 are connected to the AND gate U26, and the NAND gates U1 to U14. The part consisting of the counter part 10 corresponds to a noar gate U18, a NAND gate U15-U17, an end gate U22-U23, an inverter U24-U25, and U27, and the clock input terminal 1 The first and second clear stages 2 and 3 receive signals, and a portion formed of the flip-flop U21 corresponds to the state decoder logic unit 20.

The flip-flops U0 and U21 are four TTL logic deflip-flops, for example, 74LS175 of the US "T1" company.

3 is a state diagram of the counter portion 10 of FIG. 2 according to the present invention, and FIG. 4 is an operation timing diagram of FIG. 2 according to the present invention.

(4a) is the input clock waveform diagram of the clock input terminal (1), (4b) is the output of the output terminal (RASW0) of the flip-flop (U21) is a low address strobe (RASW0) signal when there is no DT request, ( 4c) is a column address strobe (CASW0) signal when there is no DT request as the output of the inverter U24, and (4D) is a low address strobe signal (RASW0) when there is a DT request as the output signal of the flip-flop (U21). (4e) is the column address strobe signal (CASW0) when there is a DT request to the output of the inverter U25, and thus, a specific example of the present invention will be described in detail with reference to FIGS. 1-4. After dividing 2, input the clock input terminal 1 of the flip-flop U0 with the same waveform as (4a) and latch the state of the data input terminal. The state of the output terminal QA-QD of the flip-flop U0 is The transition is shifted as shown in FIG. 3, and the states of the output terminals QA-QD of the flip-flop U0 are NAND gates U1, U3, U4-U5, U7. , U8-U9, U11-U12, U14 are inputted and logicalized, and NAND gates are logically inputted to be input to the input terminal of the flip-flop U0.

-

을 낸드게이트(U1-U17)에서 논리화하고 , 노아게이트 (U18)에서 논리화한후 디플립플롭(U21)에 입력한다. 상기 디플립플롭(U21)에서는 클럭입력단(1)의(4a)신호에 따라 래치하면 출력단(QA)으로 DT요구가 없을시 (4b)와 같은 로우 어드레스 스트로브 신호(RASW0)가 발생되고 DT요구가 있을시 (4d)신호와 같이 발생된다. 한편상기 디플립플롭(U21)의 출력단

신호를 앤드게이트(U22-U23)에 입력하여 클럭입력단(1)의 신호를 인버터(U27)에서 반전한 신호와 앤드게이트(U21,U23)에서 논리화하고 인버터(U24, U25)에서 반전하면 DT요구가 없을시 (4c)와같은 컬럼 어드레스 스트로브 신호(CASW0)가 발생되고 DT요구가 있을시(4e)신호가 발생된다.At this time, at the rising edge of the clock of the clock input terminal 1, the output of the flip-flop U0 transitions as shown in FIG. 3 and counts 12. The gray code is applied to the outputs of the output terminals QA-QD of the flip-flop U0 and their complement values.

-

Is logic at the NAND gates U1-U17, is logic at the NOR gate U18, and input to the deflip-flop U21. In the flip-flop U21, when latching according to the signal 4a of the clock input terminal 1, when there is no DT request to the output terminal QA, a row address strobe signal RASW0 such as 4b is generated and the DT request is generated. When present, it is generated together with the 4d signal. On the other hand, the output terminal of the flip-flop (U21)

When the signal is inputted to the AND gates U22 to U23, the signal of the clock input terminal 1 is inverted by the inverter U27, and is logicized by the AND gates U21 and U23 and inverted by the inverters U24 and U25. When there is no request, a column address strobe signal CASW0 such as 4c is generated, and when there is a DT request, 4e is generated.

That is, (4b) and (4c) are signals when there is no DT request, and (4d) and (4e) are signals when there is a DT request.

,

,

를 공급하여DT가 없을시는PIP 데이터를 메모리에 쓰고, DT가 있을시는 저장된 PIP저장데이타를 읽고 주화면상에 소화면으로 정확히 삽입할 수 있게 된다.The signals (4b) to (4d) and (4d) to (4e) are inputted to the selector 20 and multiplexed according to the output signal of the dual port request signal generator 40 to the dual port memory 50. Stable and Accurate Access Control Signal

,

,

If there is no DT, PIP data can be written into memory, and if there is DT, the stored PIP data can be read and inserted as a small screen on the main screen.

The first clear stage 2 uses a horizontal synchronization signal (Hsync: 63.3 kHz), and the second clear stage 3 is a main reset signal generated when the system is turned on.

As mentioned above, since the DT operation timing and the normal operation timing are generated and applied separately, stable access is possible, and all the data can be written by separating the DT writing, and the system can be modularized into one and memory access operation. There is an advantage in eliminating roadblocks and errors.

Claims (3)

In the picture-in-picture controller, in the control signal generation circuit of the dual port memory 50, an input latched output based on a clock input to the input terminal 11 and a horizontal synchronization signal is grayed out. The counter unit 10 repeats the N-bin count in a code generation method, and is connected to the output terminal of the counter unit 10 to decode the output of the counter unit 10 to perform normal and DT processing of the dual port memory 50. Generating a row and column address strobe signal and latching according to the input clock signal of the input terminal 11 to stabilize the output operation. A dual port request signal generator 40 for generating a write signal WE for writing data to the dual port memory 50 and a serial output enable signal DT for reading and outputting video data; Low and column address strobe signals connected to the output terminal of the logic unit 20

And write signal

Serial output enable signal connected to the output terminal of the dual port request generator 40

The dual-port memory control signal generation circuit of the picture-in-picture controller, characterized in that the selection unit 30 is received by receiving a selection control signal to the dual port memory 50. 2. The first and second counters of claim 1, wherein the counter unit 10 connects the clock input terminal 1 to the clear terminal CLR of the de-flop flop U0 connected to the clock terminal CK of the de-flop flop U0. The output terminal of the AND gate U26 receiving the signal of the clear terminal 23 is connected, and the output terminal QA-QD and the output terminal of the flip-flop U0 are connected.

Is connected to the input terminals of the NAND gates U1-U5 and U7 and U8, U9, U11, U12 and U14, and the output terminals of the NAND gates U1-U5 and U7 are input terminals of the NAND gates U2 and U6. The output terminals of the NAND gates U2 and U6 to the input terminals D0 and D1 of the flip-flop U0, and the output terminals of the NAND gates U8, U9, U11, U12 and U14. In the picture-in-picture controller, the output terminal of the NAND gates U10 and U13 is connected to the input terminals D2 and D3 of the deflip-flop U0. Port memory control signal generation circuit) The method of claim 1, wherein the state decoding logic unit 20 is the output terminal (QA, QB,

-QC) to the input terminal of the NAND gates (U15-U17) and the output terminals (QA, QB) of the flip-flop (U0) to the input terminal of the NOR gate (U18) and the NAND gate (U15, U17) of the The output terminal is connected to the input terminal of the NAND gate U16, the output terminal of the NOR gate U18 is connected to the input terminal U0 of the flip flop U21, and the output terminal of the NAND gate U16 is flip-flop U21. The input of the club input terminal 1 to the clock terminal CK of the flip-flop U21, and the input of the second clear stage 3 to the clear terminal CLR. And a low address strobe signal to the output terminals QA and QB of the deflip-flop U21.

Is generated and the output terminal of the deflip-flop (U21)

And the second clear stage 2 are connected to the input terminals of the AND gates U22 and U23, and the clock input terminal 1 is inputted to the AND gates U22 and U23 through the inverter U27 to supply the AND gate U22. In the picture-in-picture controller, the output of the U23 is inverted by the inverters U24 and U25 to generate the column address strobe signals CASW0 and CASWD and input the same to the selector 30. Port memory control signal generation circuit.

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