KR910007253Y1 - Switching circuit of image head - Google Patents

Abstract

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Description

Image Head Switching Circuit

1 is a conventional switching circuit diagram.

2 is a switching circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

11, 12: amplifier 13: level detector

14: comparator SW ₁₁ , W ₁₂ : switch

SW ₁₃ , W ₁₆ : Electronic switch CH _11a , CH _11b , CH _21a , CH _21b : Image head

AND ₁₁ -AND ₁₄ : AND gate I ₁₁ , I ₁₂ : Inverter

SPH ₁₁ : Constant speed mode control signal input terminal ATH ₁₁ : Shift mode control signal input terminal

HSW ₁₁ : Head Switching Signal Input Terminal

The present invention relates to an image head switching circuit in which four image heads are installed in a rotating head drum, and the four image heads selectively output respective reproduced image signals while tracing the video tape.

In the conventional image head switching circuit, as shown in FIG. ₁ , one terminal of the image heads CH _1a and CH _1b dedicated to the constant speed mode and the image heads CH _2a and CH _2b dedicated to the long time mode is connected to the ground switch SW. ₁₎ (connected to the SW _2), the other terminal amplifier (1,2) (3,4) to (SW each of the electronic switch (SW ₃₎ the head switching signal input terminal (HSW ₁₎ connected to a control terminal and then through ₄ ) respectively connected to one side and the other fixed terminal (a ₃ , b ₃ ) (a ₄ , b ₄ ), and the movable terminal of the electronic switch (SW ₃ ) (SW ₄ ) and one side of the electronic switch (SW ₅ ) It is connected to the other fixed terminal (a ₅ ) (b ₅ ) and is connected to the non-inverting and inverting input terminals (+) (-) of the comparator 11 through the level detectors 5 and 6, and the comparator 7. the output of the post through the shift mode control signal input terminal (ATH ₁₎ and with soon as connected to the input terminal of the aND gate (aND ₁₎ as well as an inverter (I ₁₎ that the transmission mode control signal input terminal (ATH ₁₎ the constant speed De output terminal of the control signal input terminal (SPH ₁₎ and the AND gate (AND ₁₎ (AND ₂₎ with self-through diode (D ₁₎ (D ₂₎ is connected to the control terminal of the electronic switch (SW _5).

Switch (SW _1, SW ₂₎ In the above paragraph, is reproducing, the switch (SW ₃ -SW ₅₎ has a side fixed terminal end to the movable when applied with the high potential to the control terminal (a ₃ -a ₅₎ short-circuited to the The shift mode control signal input terminal ATH ₁ is input in the case of regeneration in the shift mode, that is, in the shift mode such as high speed playback or low speed playback, and the constant speed mode control signal input terminal SPH ₁ is constant speed. High potential is input when playing in the mode.

In the conventional video head switching circuit configured as described above, the switch SW ₁ (SW ₂ ) is shorted when the video tape is reproduced, and the video heads CH _1a and CH _1b (CH _2a and CH _2b ) trace the video tape. When the video signal is reproduced, the reproduced video signal is amplified by the amplifiers (1, 2) (3, 4) so that one side and the other fixed terminal (a ₃ , b ₅ ) of the electronic switch (SW ₃ ) (SW ₄ ). (a ₄ , b ₄ ), and at this time, the 30HZ head switching signal input to the head switching signal input terminal (HSW ₂ ) is applied to the control terminal of the electronic switch (SW ₃ ) (SW ₄ ), so that the electronic switch (SW _3). ), The output signal of the amplifiers (1, 2) (3, 4) is switched to the electronic switch (SW) as the movable terminal of (SW ₄ ) is cut to one side and the other fixed terminal (a ₃ , b ₅ ) (a ₄ , b ₄ ). ₃₎ (it is rolled through SW _4), soon as applied to the electronic switch (SW ₃₎ (one side and the other side fixed terminal of the signal is an electronic switch (SW ₅₎ through _{SW 4) (a 5) (} b 5) as well as re The level is detected by the bell detectors (5) and (6), and the detected level is input to the non-inverting and inverting input terminals (+) (-) of the comparator (7) so that the comparator (7) has an image head ( CH _1a , CH _1b ) (CH _2a , CH _2b ) output high and low potentials according to the magnitude of the video signal reproduced.

At this time, when playing in the constant speed mode, the high potential is inputted to the constant speed mode control signal input terminal SPH ₁ and applied to one input terminal of the AND gate AND ₂ , and the low potential to the shift mode control signal input terminal ATH ₁ . is inputted, it is applied to one side input terminal of the AND gate (AND ₁₎ as well as the inverter is inverted to the high potential via the (I _1), so applied to the other input terminal of the AND gate (AND ₂₎ the AND gate (AND ₂₎ is the high potential Since the high potential is applied to the control terminal of the electronic switch SW ₅ through the diode D ₂ , the movable terminal of the electronic switch SW ₅ is short-circuited to one side fixed terminal a ₅ so that the image head ( The video signals reproduced by CH _1a and CH _1b ) are output.

In the long time mode, the low potential is input to both the constant speed mode and the shift mode control signal input terminal SPH ₁ (ATH ₁ ) and applied to one pressure terminal of the AND gate AND ₂ (AND ₁ ). gate (aND ₂₎ (aND ₁₎ both being applied with the low potential to the control terminal of the output to low potential electronic switch (SW _5), yiettara movable terminal is the other fixed terminal (b ₅₎ of the electronic switch (SW ₅₎ The video signal reproduced by the video heads CH _2b and CH _2b is short-circuited.

In addition, when viewed in transmission mode is a high-potential input to the shift mode control signal input terminal (ATH ₁₎ so applied to the AND gate (AND _1), the AND gate (AND ₁₎ is high and low in accordance with the output signal of the comparator 7 Outputs the upper and lower potentials and is applied to the control terminal of the electronic switch SW ₅ through the diode D _1. Accordingly, in the image signal reproduced by the image heads CH _1a and CH _1b (CH _2a and CH _2b ). The video signal having a large level is output through the electronic switch SW ₅ .

However, such a conventional video head switching circuit requires four amplifiers by amplifying the video signals reproduced by the four video heads respectively, and the circuit configuration has to be detected and compared with two level detectors. There was a complex flaw.

The present invention has been conceived of a simple configuration of a circuit for switching an image head using two amplifiers and one level detector in view of such a conventional defect, which will be described in detail with reference to the accompanying drawings of FIG. same.

First as a video head switching circuit of the subject innovation turns 2, whereby the video head of a constant speed as shown mode and long time mode only (CH _11a, CH _21b) grounding switch to one terminal of the _{(CH 21a, CH 21b) (} SW 11) (SW ₁₂ ), and the other terminal of the image heads CH _11a and CH _21a (CH _21b and CH _21b ) is fixed to one side and the other fixed terminal (a ₁₃ and b ₁₃ ) of the electronic switch SW ₁₃ (SW ₁₄ ). ) (a _14, b ₁₄₎ an electronic switch (SW ₁₃₎ (SW ₁₄₎ the movable terminal of the electronic switch via an amplifier (11) (12) (SW 15) side and the other side fixed terminal (a ₁₅ of connecting to) (B ₁₅ ), the output terminal of the amplifier 11 is connected to the non-inverting input terminal (+) of the comparator 14 through the level detector 13, and the inverting input terminal (−) of the comparator 14 is connected. ) Is connected to the connection points of the resistors R ₁₁ and R ₁₂ connected in series to the power supply terminal Vcc, while the shift mode control signal input terminal ATH _{11 is} connected to the head switching signal input terminal HSW ₁₁ and the comparator. (14) Output terminal and the hamkkae AND gate (AND ₁₂₎ (AND ₁₃₎ input terminals in the junction box and addition constant-speed mode control signal input terminal (SPH ₁₁₎ through a variable speed mode control signal input terminal (ATH ₁₁₎ an inverter (I ₁₁₎ of the and the head switching signal input terminal (HSW ₁₎ and along the aND gate (aND ₁₁₎ (aND ₁₄₎ connected to the input terminal of and, an output terminal of the aND gate (aND _11, aND ₁₂₎ the diode (D _11, D ₁₂₎ The electronic switch SW ₁₃ is connected to the control terminal of the electronic switch SW ₁₃ , and the output terminal of the AND gate AND ₁₁ is connected to the inverter I ₁₂ and the control terminal to the shift mode control signal input terminal ATH ₁₁ . It is connected to the control terminal of the electronic switch SW ₁₄ through the diode D ₁₃ (D ₁₄ ) together with the output terminal of the AND gate AND ₁₂ through the switch SW _1b , and the AND gate AND ₁₃ . The output terminal of (AND ₁₄ ) is connected to the control terminal of the electronic switch SW ₁₅ through the diode D ₁₅ and D ₁₆ . In this case, the switches SW ₁₁ and SW ₁₂ are short-circuited when regenerating, and the electronic switches SW _13- SW ₁₅ are movable terminals having one side fixed terminal (a ₁₃₎ when a high potential is applied to the control terminal. -a ₁₅ ), the switch SW ₁₆ is opened when a high potential is applied to the control terminal, and the constant speed and shift mode control signal input terminals SPH ₁₁ (ATH ₁₁ ) are reproduced in the constant speed mode and the shift mode. In each case, a high potential is input.

According to the present invention configured as described above, when power is applied to the power supply terminal Vcc, the power is divided by the resistors R ₁₁ and R ₁₂ to apply a constant reference voltage to the inverting input terminal (-) of the comparator 14. , When playing, the switches SW ₁₁ and SW ₁₂ are short-circuited and the video signals reproduced by the meditation heads CH _11a and CH _21b (CH _11b and CH _21b ) from the videotape are _converted to the electronic switch SW ₁₃ (SW ₁₄ ). The short circuit is shorted to one side and the other fixed terminal (a ₁₃ , b ₁₃ ) (a ₁₄ , b ₁₄ ) of the

At this time, in the case of the reproduction in the constant speed mode, the high potential is input to the constant speed mode control signal input terminal SPH ₁₁ and applied to one input terminal of the AND gate AND ₁₁ , and the shift mode control signal input terminal ATH ₁₁ is performed. The low potential is input to the furnace to short-circuit the electronic switch SW ₁₆ , and the low potential is applied to the other input terminal of the AND gate AND ₁₂ (AND _l3 ), and is inverted to high potential through the inverter I ₁₁ . Since it is applied to the other input terminal of the AND gate AND ₁₁ (AND ₁₄ ), the AND gate AND ₁₁ outputs a high potential, and the AND gates AND ₁₂ and AND ₁₃ are related to a signal applied to the one input terminal thereof. The low potential is output without the AND gate AND ₁₄ and is input to the head switching signal input terminal HSW ₁₁ to output a 30HZ head switching signal applied to one input terminal thereof.

Accordingly, the movable terminal is a classical terminal (a ₁₃₎ one side of the electronic switch (SW ₁₃₎ the control terminal of the AND gate (AND ₁₁₎ with a high potential is applied through the diode (D ₁₁₎ an electronic switch (SW ₁₃₎ output from the And a high potential output from the AND gate AND ₁₁ is inverted to a low potential through the inverter I ₁₂ , and then applied through the electronic switch SW ₁₆ to the control terminal of the electronic switch SW ₁₄ . Since the low potential output from the gate AND ₁₂ is applied, the movable terminal of the electronic switch SW ₁₄ is shorted to the other fixed terminal b ₁₄ , and the AND gate AND ₁₄ is connected to the control terminal of the electronic switch SW ₁₅ . Since the head switching signal outputted from is applied and the movable terminal is switched according to the head switching signal, the video signal reproduced by the video heads CH _11a and CH _11b is transferred to the amplifier 11 through the electronic switch SW ₁₃ (SW ₁₄ ). (12) is inputted and amplified and then merged through an electronic switch (SW ₁₅ ). That output.

In case of playing in the long time mode, the low potential is inputted to the constant speed mode control signal input terminal SPH ₁₁ and applied to one input terminal of the AND gate AND ₁₁ , and the low potential is supplied to the shift mode control signal input terminal ATH ₁₁ . The potential is inputted, the electronic switch SW ₁₆ is short-circuited, and the low potential is applied to the other input terminal of the AND gates AND ₁₂ and AND ₁₃ , and is inverted to a high potential through the inverter I ₁₁ , thereby ending the AND gate. Since AND gate ₁₁ is applied to the other input terminal of AND ₁₁ and AND ₁₄ , the AND gate AND ₁₁ outputs a low potential, and the low potential is applied to the control terminal of the electronic switch SW ₁₃ through the diode D ₁₁ . after the movable terminal of the electronic switch (SW ₁₃₎ short-circuited as soon as well as a low-potential output from the AND gate (AND ₁₁₎ inverted to the high potential via an inverter (I ₁₂₎ to its other side fixed terminal (b ₁₃₎ the diode (D ₁₃ ) to the control terminal of the electronic switch (SW ₁₄₎ through It is is short-circuited to the electronic switch the movable terminal side fixed terminal (a ₁₄₎ of the (SW ₁₄₎ is, the AND gate (AND _12, AND ₁₃₎ outputs a low potential, the AND gate (AND ₁₄₎ is a head switching signal input terminal is input to the (HSW ₁₁₎ so through the outputs of the head switching signal which is applied to its one input diode (D ₁₆₎ applied to the control terminal of the electronic switch (SW ₁₅₎ an electronic switch (SW ₁₅₎ of the head switching signal Is switched accordingly.

Accordingly, the image signals reproduced by the image heads CH _21a and CH _21b are input to the amplifiers 11 and 12 through the switches SW ₁₃ and SW ₁₄ , and then amplified and switched according to the head switching signal. Combined and output through the switch (SW ₁₅ ).

In addition, when reproducing in the shift mode, the low potential is input to the constant speed mode control signal input terminal SPH ₁₁ and applied to one input terminal to the AND gate AND ₁₁ , and the high speed is transmitted to the shift mode control signal input terminal ATH ₁₁ . The upper side is inputted, the electronic switch SW ₁₆ is opened, and the high potential is applied to the other input terminal of the AND gates AND ₁₂ and AND ₁₃ , and the inverter is inverted to a low potential through the inverter I ₁₁ so that the AND gate ( AND ₁₁ and AND ₁₄ are applied to the other input terminal, so the AND gates AND ₁₁ and AND ₁₄ output low potentials, and the AND gate AND ₁₂ is input to the head switching signal input terminal HSW ₁₁ and one side thereof. Outputs the head switching signal applied to the input terminal, the output head switching signal is applied to the control terminal of the electronic switch (SW ₁₃ , SW ₁₄ ) through the diode (D ₁₂ , D ₁₄ ), the electronic switch (SW ₁₂ , SW ₁₄₎ is in accordance with the head switching signal And ring, yiettara video heads (CH _11a, CH _11b) (CH _21a, CH _21b), the electronic switch according to the reproduced video signal is the head switching signal (SW ₁₃₎ (SW _14), the amplifiers 11 and 12 through and then is input to the amplifier is applied to each electronic switch one side and the other side fixed terminals _{(SW 15) (a 15)} (b 15).

Since the output signal of the amplifier 11 is input to the level detector 13 and the level is detected, the output signal of the amplifier 11 is input to the non-inverting input terminal (+) of the comparator 14, so that the comparator 14 is a power source of the power supply terminal Vcc. The reference voltage divided by the resistors R ₁₁ and R ₁₂ is compared with the output signal of the level detector 13, and a high potential or a low potential is output to the output terminal thereof, wherein the output level of the level detector 13 is referenced. When the voltage is higher than the voltage, the comparator 14 outputs a high potential, the AND gate AND ₁₃ outputs a high potential, and a high potential is applied to the control terminal of the electronic switch SW ₁₅ so that its movable terminal has one fixed terminal. (a ₁₅ ), the output signal of the amplifier 11 is output through the switch SW ₁₅ , and when the output level of the level detector 13 is lower than the reference voltage, the comparator 14 outputs a low potential. the aND gate (aND ₁₃₎ that outputs a low potential, the control terminal of the electronic switch (SW ₁₅₎ It is applied with the low potential to the movable terminal so that his short-circuit to the other fixed terminal ₍₁₅ b), the output signal of the amplifier ₁₂ is output via a switch (SW _15).

As described in detail above, the present invention uses two amplifiers and one level detector to switch the image signals reproduced by the four image heads, respectively, thereby reducing the production cost of the product.

Claims (1)

A video head switching circuit for switching video signals reproduced by four video heads (CH _11a , CH _11b ) (CH _21a , CH _21b ), respectively, wherein the video heads (CH _11a , CH _21b ) (CH _21a , CH _11b). ) Is connected to one side and the other fixed terminal (a ₁₃ , b ₁₃ ) (a ₁₄ , b ₁₄ ) of the electronic switch (SW ₁₃ ) (SW ₁₄ ), and the movable terminal of the switch (SW ₁₃ ) (SW ₁₄ ) is an amplifier. (11) Connect one side and the other fixed terminal (a ₁₅ ) (b ₁₅ ) of the switch (SW ₁₅ ) through (12), and the output terminal of the amplifier 11 times through the level detector (13), and then inverted While connected to the non-inverting input terminal (+) of the comparator 14 to which the reference voltage is applied to the input terminal (-), the shift mode control signal input terminal ATH _{11 is} connected to the head switching signal input terminal HSW ₁₁ and the the aND gate (aND ₁₂₎ (aND _13), the constant-speed mode control signal input terminal and the box as well as the input terminal (ATH ₁₁₎ connected to an input terminal via an inverter (I ₁₁₎ together with the output terminal of the comparator 14 (SPH ₁₁₎ and a head switching signal input terminal (HSW ₁₁₎ and AND gate (AND ₁₁₎ the electronic switch output chairs connected to the input terminal, and the AND gate (AND ₁₁₎ (AND ₁₂₎ of the (AND ₁₂₎ with ( The AND gate is connected to the control terminal side of SW ₁₃ ) and the output terminal of the AND gate AND ₁₁ is connected to the inverter I ₁₂ and the control terminal through an electronic switch SW ₁₆ having the input terminal ATH ₁₁ connected to the control terminal. and with the output terminal side of the (aND ₁₂₎ connected to a control terminal side of the electronic switch (SW _14), the aND gate (aND ₁₃₎ An output terminal of the (aND ₁₄₎ connected to the control terminal side of the electronic switch (SW ₁₅₎ Image head switching circuit, characterized in that configured to.