KR910006566Y1 - Audio mute circuit - Google Patents

Audio mute circuit Download PDF

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Publication number
KR910006566Y1
KR910006566Y1 KR2019860016850U KR860016850U KR910006566Y1 KR 910006566 Y1 KR910006566 Y1 KR 910006566Y1 KR 2019860016850 U KR2019860016850 U KR 2019860016850U KR 860016850 U KR860016850 U KR 860016850U KR 910006566 Y1 KR910006566 Y1 KR 910006566Y1
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terminal
circuit
resistor
signal
connect
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KR2019860016850U
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Korean (ko)
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KR880008495U (en
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김흥섭
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대우전자 주식회사
김용원
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control
    • H04N5/505—Invisible or silent tuning

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)

Abstract

내용 없음.No content.

Description

음성 뮤트(AUDIO MUTE)회로AUDIO MUTE CIRCUIT

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 종래의 회로도.2 is a conventional circuit diagram.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

HD PULSE : 수평동기 신호단자 AUDIO OUT : 출력단자HD PULSE: Horizontal Sync Signal Terminal AUDIO OUT: Output Terminal

A : 아이씨 AMP : 증폭회로A: IC AMP: Amplification Circuit

DETELTOR : 검출회로 PLL : PLL회로DETELTOR: Detection Circuit PLL: PLL Circuit

C1-C6: 콘덴서 R1-R4: 저항C 1 -C 6 : Capacitor R 1 -R 4 : Resistance

Q1, Q2: 트랜지스터 VR : 가변저항Q 1 , Q 2 : Transistor VR: Variable resistor

본 고안은 VTR에 입력신호가 없을때 음성신호를 뮤트(MUTE)할수 있도록한 뮤팅(MUTING)회로에 관한 것으로서 특히 음향 아이씨(TONE DECODER IC)를 이용한 음성 뮤트(AUDIO MUTE)회로에 관한 것이다.The present invention relates to a muting circuit that can mute a voice signal when there is no input signal in the VTR, and more particularly, to an audio mute circuit using a TONE DECODER IC.

일반적으로 TV나 VTR에 입력신호가 없을때 음성 뮤트(AUDIO MUTE)기능을 갖는 회로로서 서독에서는 이미 오래전부터 TV나 VTR에 뮤트 기능을 갖는 규정 FTZ(不要輻射에 관한 규정)을 정하여 이에 대한 회로가 수없이 공개되고 있으나 제2도에 도시된 바와 같이 트랜지스터로 구성되어 있어 주변회로가 복잡하고 그에 따른 넓은 공간을 차지하는 문제점이 제기 되었다.Generally, a circuit having an audio mute function when there is no input signal to a TV or a VTR. In West Germany, a regulation FTZ (a regulation on a requirement) having a mute function on a TV or a VTR has been established for a long time. Although it has been disclosed numerous times, since it is composed of transistors as shown in FIG.

이에 제2도를 위시하여 간력히 설명하면 도시된 바와 같이 PIF VIDEO 출력(미도시) 신호가 트랜지스터(Q1)의 에미터(A')에 연결된다. 트랜지스터(Q2, Q3)에서는 방송신호가 없을때에 동기 신호만 Pick up (픽엎)하여 트랜지스터(Q6)의 콜렉터를 LOW레벨로 유지시켜 준다.2, the PIF VIDEO output signal (not shown) is connected to the emitter A 'of the transistor Q 1 . In the transistors Q 2 and Q 3 , when there is no broadcast signal, only the synchronization signal is picked up to keep the collector of the transistor Q 6 at a low level.

이 출력된 신호가 트랜지스터(Q7, Q8)에 의해 뮤트 신호인 로우(LOW)신호가 트랜지스터(Q8)의 콜렉터에서 출력됨으로서 방송신호가 뮤트되도록 설계하였으나 종래의 오디오 뮤트 회로는 다수개의 트랜지스터를 사용함으로서 주변 회로가 복잡하고 이에 따른 PCB에 부착공간을 많이 차지하게 되며, 또한 다수개의 부품을 사용함으로서 생산 코스트가 높아지는 문제점이 제기 되었다.The output signal is designed to mute the broadcast signal by outputting the low signal, which is a mute signal by the transistors Q 7 and Q 8 , from the collector of the transistor Q 8. However, the conventional audio mute circuit uses a plurality of transistors. By using, the peripheral circuit is complicated and thus occupies a lot of space for attachment to the PCB, and the problem of raising the production cost by using a plurality of components has been raised.

이에 본 고안의 목적은 상기와 같은 문제점을 해결코져 음향기기에 사용되는 음향 아이씨(TONE DECODER IC)를 사용한 것으로서, 이를 첨부된 도면에 의거 설명하면 다음과 같다.Therefore, the object of the present invention is to use the acoustic IC (TONE DECODER IC) used in the audio device to solve the problems as described above, it will be described based on the accompanying drawings as follows.

제1도는 본 고안의 회로도로서 증폭회로(AMP), 검출회로(DETECTOR), PLL 회로(PLL) 및 트랜지스터(Q2)로 구성된 멜로디 아이씨(A)의 단자(1, 2)에 콘덴서(C1, C2)를 병렬 연결하여 접속하고 단자(3)에 수평동기 신호단자(HD PULSE)를 접속하며 단자(4)에 콘덴서(C4)를 접속하여 구성한다.FIG. 1 is a circuit diagram of the present invention, and the capacitor C 1 is connected to the terminals 1 and 2 of the melody IC A composed of an amplifier circuit AMP, a detector circuit, a PLL circuit PLL, and a transistor Q 2 . , C2 are connected in parallel, the horizontal synchronous signal terminal (HD PULSE) is connected to the terminal (3), and the condenser (C 4 ) is connected to the terminal (4).

또한 그의 단자(5)와 단자(6) 사이에 저항(R2)와 가변저항(VR)을 직렬연결하되 그 사이에 콘덴서(C5)와 제너다이오드(ZD) 및 저항(R1)을 연결하여 단자(8)에 접속하며 그 사이에 트랜지스터(Q1)의 베이스를 접속하고 콘덴서(C6)와 저항(R4)를 병렬 연결하여 구성한다.In addition, a resistor (R 2 ) and a variable resistor (VR) are connected in series between the terminal (5) and the terminal (6), and a capacitor (C 5 ), a zener diode (ZD), and a resistor (R 1 ) are connected between them. And the base of transistor Q 1 is connected between them, and capacitor C 6 and resistor R 4 are connected in parallel.

이와 같이 구성된 본 고안의 특징인 점은 증폭회로(AMP), 검출회로(DETECTOR), PLL 회로(PLL)로 구성된 8PIN의 소형 음향 아이씨를 설치한 점이 특징이 있다.A feature of the present invention, which is configured as described above, is characterized by the fact that an 8PIN small acoustic IC comprising an amplifier circuit (AMP), a detector circuit (DETECTOR), and a PLL circuit (PLL) is installed.

이하 본 고안의 작용효과를 설명하기전에 멜로디 아이씨에 대하여 먼저 설명하게 되면 단자(1)는 출력필터(OUTPUT FILTER)이고 단자(2)는 루우프 필터(LOOP FILTER)이다.Before describing the effects of the present invention, the melody IC will be described first. The terminal 1 is an output filter and the terminal 2 is a loop filter.

단자(3)은 입력단자로서 수평동기 펄스(HD PULSE)가 입력하게 된다.The terminal 3 is inputted with a horizontal synchronization pulse HD PULSE as an input terminal.

이 수평동기 펄스의 크기는 집적회로(IC)의 설계상 200[mV rms] 이하로 되어 있다.The magnitude of this horizontal synchronization pulse is 200 [mV rms] or less in the design of the integrated circuit (IC).

또한 수평동기 펄스는 본 회로에서는 팔(PAL) 수평동기 신호 주파수인 15.625 [KHZ]를 사용하였다.The horizontal synchronous pulse is 15.625 [KHZ], which is the PAL horizontal synchronous signal frequency.

단자(4)는 전원(Vcc)으로서 4.75V에서 9V로 인가하게 되어 있는데 5.1V의 제너다이오드(ZD)를 사용하여 12V가 인가되면 5V를 유지할 수 있도록 하였다.The terminal 4 is applied as a power supply (Vcc) from 4.75V to 9V. When 12V is applied using a 5.1V zener diode (ZD), 5V can be maintained.

단자(5)와 단자(6)에 연결되는 저항(R2, R5)과 콘덴서(C5)는 시정수를 결정하는 소자로서 다음 수식에 의해 주파수가 결정된다.The resistors R 2 and R 5 and the capacitor C 5 connected to the terminal 5 and the terminal 6 determine the time constant, and the frequency is determined by the following equation.

(fo = 수평동기주파수, R : R2+R5(콘덴서 용량) 여기에서 콘덴서(C5)는 온도특성에 강한 마일라 콘덴서(Mylar Condenser)를 사용하였다. (fo = horizontal synchronizing frequency, R: R 2 + R 5 (capacitor capacity) Here, the condenser (C5) uses a Mylar condenser, which is resistant to temperature characteristics.

단자(7)은 접지(Ground)이고 단자(8)는 출력단자로서 방송신호가 있을때는 로우(LOW)신호를 방송신호가 없을때는 하이(High) 신호를 유지시켜 주게된다.The terminal 7 is ground, and the terminal 8 is an output terminal that maintains a low signal when there is a broadcast signal and a high signal when there is no broadcast signal.

따라서 수평동기 신호단자(HD PULSE)에 동기 신호가 입력시에는 아이씨(A)의 암프회로(AMP)에 의해 증폭되어 트랜지스터(Q2)의 베이스에 인가되어 턴온하게 됨으로서 공급전원(Vcc)이 저항(R3)을 통할때 제너다이오드(ZD)의 정격전압에 의해 5V의 전원이 저항(R1)을 통하여 트랜지스터(Q2)의 콜렉터와 에미터에 흐르게 된다.Therefore, when a synchronous signal is input to the horizontal synchronous signal terminal HD PULSE, the amplification circuit AMP of the IC A is amplified and applied to the base of the transistor Q 2 so that the power supply Vcc is turned on. When (R 3 ) is passed, a 5V power supply flows through the resistor (R 1 ) to the collector and emitter of the transistor (Q 2 ) by the rated voltage of the zener diode (ZD).

이에 그의 접속된 트랜지스터(Q1)의 베이스에는 로우 전위가 될때 그의 콜렉터는 공급전압(하이상태)에 가까운 전위가 되어 정상적인 동작을 하게 된다.At the base of the transistor Q 1 connected thereto, when the low potential is reached, the collector becomes a potential close to the supply voltage (high state), thereby performing normal operation.

그러나, 수평동기 신호단자(HD PULSE)에 신호가 없을때에는 아이씨(A)의 트랜지스터(Q2)는 오프됨으로서 공급전원(Vcc)은 제너다이오드(ZD)에 의한 정격전압이 저항(R1)을 통하여 뮤팅 트랜지스터(Q1)에 공급됨으로 뮤팅 트랜지스터(Q1)가 도통되며 그의 출력단자(AUDIO OUT)의 전위는 로우가 되어 신호를 뮤트시키게 된다.However, when there is no signal at the horizontal synchronous signal terminal HD PULSE, the transistor Q 2 of the IC A is turned off, so that the supply voltage Vcc is rated at the resistor R 1 by the zener diode ZD. The muting transistor Q 1 is turned on by being supplied to the muting transistor Q 1 , and the potential of the output terminal AUDIO OUT becomes low to mute the signal.

이상에서와 같이 본 고안은 종래의 뮤트회로에 있어서 다수개의 트랜지스터를 사용함으로서 그에 따른 주변회로가 복잡하고, PCB의 부착공간을 많이 차지하는 단점을 해결함으로서 생산원가의 다운(DOWN) 및 회로를 간단하게 하는 효과가 있다.As described above, the present invention uses a plurality of transistors in a conventional mute circuit, thereby simplifying the down-circuit of the production cost and the circuit by solving a disadvantage that the peripheral circuit is complicated accordingly and occupies a lot of the attachment space of the PCB. It is effective.

Claims (1)

통상의 방송신호 뮤트회로에 있어서 공지의 증폭회로(AMP), 검출회로(DETECTOR), PLL회로(PLL)로서 구성된 음향아이씨(A : LM 567C)의 단자(3)에 수평동기 신호단자(HD PULSE)를 접속하며, 단자(4)에 콘덴서(C4)를 접속하고, 또한 그의 단자(5)와 단자(6)사이에 저항(R2)과 가변저항(VR)을 직렬연결하되 그 사이에 콘덴서(C5)와 제어다이오드(ZD) 및 저항(R1)을 연결하여 단자(8)에 접속하여 그 사이에 트랜지스터(Q1)의 베이스를 접속하고 콘덴서(C6)와 저항(R4)를 병렬 연결하고 구성하는 것을 특징으로 하는 음향 아이씨를 이용한 음성뮤트회로.In a conventional broadcast signal mute circuit, a horizontal synchronous signal terminal (HD PULSE) is connected to a terminal 3 of an acoustic IC (A: LM 567C) configured as a known amplifier circuit (AMP), detection circuit (DETECTOR), and PLL circuit (PLL). ), Connect a capacitor (C 4 ) to the terminal (4), and connect a resistor (R 2 ) and a variable resistor (VR) in series between the terminal (5) and the terminal (6), Connect the capacitor (C 5 ), the control diode (ZD), and the resistor (R 1 ) to the terminal (8), connect the base of the transistor (Q 1 ) therebetween, and connect the capacitor (C 6 ) and the resistor (R 4). ), A voice mute circuit using an acoustic IC, characterized in that the parallel connection and configuration.
KR2019860016850U 1986-10-31 1986-10-31 Audio mute circuit KR910006566Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019860016850U KR910006566Y1 (en) 1986-10-31 1986-10-31 Audio mute circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019860016850U KR910006566Y1 (en) 1986-10-31 1986-10-31 Audio mute circuit

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KR880008495U KR880008495U (en) 1988-06-29
KR910006566Y1 true KR910006566Y1 (en) 1991-08-26

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Application Number Title Priority Date Filing Date
KR2019860016850U KR910006566Y1 (en) 1986-10-31 1986-10-31 Audio mute circuit

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