KR910005381B1 - Method and apparatus for ragion distinction of virtual memory - Google Patents

Abstract

The circuit accesses the different storage region with indirect addressing method in the digital system including the virtual memory so that the virtual memory capacity is extented more than the address capacity of the present using processor. The method comprises a selection process of storage region for selecting the region with the page unit, and a control process of the storage region for enabling the one of storage regions to the access wait state by latching the data on the data line.

Description

Region Classification Method and Circuit of Virtual Memory

1 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

10: CPU MB1-MBn: Memory Board

FF1-FFn: flip-flop G1-Gn: negative logic element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital system having a virtual memory, and in particular, an area classification method of a virtual memory device that accesses different storage areas by indirect addressing by the same address. And providing a circuit.

In general, a virtual memory device refers to an auxiliary memory device in which a plurality of memory boards, which are extended memory devices, are separately installed to expand storage capacity of a main memory device of a digital system having a processor. The conventional method of classifying a storage area of a virtual memory device is to classify a storage area of the expansion memory device by a address that is separated from an address that is currently referenced by a processor in progress, that is, an address that is available in an actual main memory device. It was. Therefore, the storage capacity of the conventional virtual memory device has been limited by the expansion of the address capacity of the processor currently in use.

Accordingly, an object of the present invention is to provide an area classification method and a circuit of a virtual memory device capable of extending the storage capacity of the virtual memory device beyond the expansion limit by the address capacity of the processor currently being used.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of the present invention, a central processing unit (CPU) 10 for controlling and controlling a system, and a plurality of memory boards MB1 for storing information processed by the CPU 10. -A single flip to control the operation of the plurality of memory boards MB1-MBn connected to the MBn and the data output terminals D0-Dn-1 of the CPU 10, respectively. It consists of a number of board control means consisting of a flop FF1-FFn and a negative logic element G1-Gn.

The present invention will be described in detail with reference to FIG. First, the CPU 10 inputs one of the plurality of negative logic elements G1 -Gn through a board selection terminal BS to access the expansion memory boards MB1-MBn. Select one of the plurality of memory boards (MB1-MBn) by applying it to the terminal, and then select one of the plurality of data output terminals (D0-Dn-1) to select any one of the plurality of memory boards (MB1-MBn). High logic logic data is output to one data output terminal corresponding to the board, and low logic logic data is output to the other data output terminals, thereby providing input terminals (FD1-FDn) of a plurality of flip-flops (FF1-FFn). One of the plurality of memory boards MB1-MBn by applying to the clock terminal CLK1-CLKn of the plurality of flip-flops FF1-FFn through the trigger signal output terminal CT. Select.

At this time, the CPU 10 writes the currently accessed memory board or the stored memory board in the form of a flag in a register or memory built therein so that confusion does not occur when the memory boards are accessed again later. . The plurality of flip-flops FF1-FFn output data on the CPU 10 corresponding to the respective input terminals FD1-FDn when a pulse-like trigger signal is applied to each clock terminal CLK1-CLKn. The logic data of the terminals D0-Dn-1 are input to each output terminal Q1-Qn, and then each of the plurality of negative logic elements G1-Gn connected to the output terminals Q1-Qn. Output to one input terminal.

Then, the plurality of negative logic elements G1-G2 input a board selection signal, which is the output of the board selection terminal BS of the CPU 10, in common through one input terminal and correspond to each other through the other input terminal. Input the outputs of the flip-flops FF1-FF2 and perform the negative logic operation on the input signals on the two input terminals, and then apply them to the corresponding memory boards MB1-MBn, respectively. Will be controlled.

The negative logic elements G1 -Gn generate a low logic output only when both input signals are in a high logic state, and when either input signal of the two input signals is in a low logic state, the negative logic elements G1 -Gn are in a high logic state. Generate the output.

Then, each of the memory boards MB1-MBn corresponding to the plurality of negative logical elements G1 -Gn is enabled when the output of the corresponding negative logical element is in a low logic state. Operate in an accessible state.

Table 1 shows a state in which the memory boards MB1-MBn are selected by the output of the data output terminals D0-Dn-1.

TABLE 1

In Table 1, '0' denotes a low logic state, '1' denotes a high logic state, and G1-Gn denotes outputs of negative logical elements G1-Gn. The memory boards MB1-MBn have the maximum capacity of one page unit, but are not shown in the figure, but have separate address input ports and data ports to be connected to the CPU 10 and to addresses applied to the address ports. By storing the page-based storage area in detail, the information processed by the CPU 10 is stored in the specifically divided storage area or the pre-stored information is read and output to the CPU 10. The flip-flops FF1 to FFn are used as latch elements for latching and outputting 1-bit data of the CPU 10 by a trigger signal in the form of a pulse.

As described above, the present invention has an advantage in that the storage capacity of the expansion memory board can be extended beyond the limit of the address capacity by dividing the storage area of the expansion memory by using the data of the ongoing processor.

Claims (3)

In a digital system having a processor and a virtual memory device, when the virtual memory device is selected, the processor outputs data through a plurality of data lines and outputs a trigger signal in the form of a pulse through a trigger line, thereby providing a page unit of the virtual processing device. A plurality of pages of the virtual memory device by latching data on the plurality of data lines by a storage area selection process of selecting a storage area of the storage area and a trigger signal on the trigger line output in the storage area selection process and then applying the data to the virtual memory device. An area classification method of a virtual memory device, characterized in that the storage area control process enables one of the unit storage areas to be in an access standby state. In a digital system having a CPU 10 for controlling a system and a plurality of expansion memory boards MB1-MBn for storing the processed information on the CPU 10, Virtual memory device comprising a plurality of board control means connected to the data output terminal (D0-Dn-1), respectively, and controls the operation of a plurality of memory boards (MB1-MBn) that are connected when the memory board is selected. Domain separation circuit. 3. A latch element according to claim 2, wherein a board control means latches and outputs logic data of a corresponding data line on the CPU 10 by a trigger signal applied from the CPU 10, an output of the latch element, and And a logical operation element configured to perform a logic operation on the output of the board selection terminal of the CPU (10) and apply it to a correspondingly connected expansion memory mode.

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