KR910005158A - FDD index correction circuit - Google Patents

FDD index correction circuit Download PDF

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Publication number
KR910005158A
KR910005158A KR1019890011091A KR890011091A KR910005158A KR 910005158 A KR910005158 A KR 910005158A KR 1019890011091 A KR1019890011091 A KR 1019890011091A KR 890011091 A KR890011091 A KR 890011091A KR 910005158 A KR910005158 A KR 910005158A
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KR
South Korea
Prior art keywords
duty cycle
cycle determination
capacitor
correction circuit
resistor
Prior art date
Application number
KR1019890011091A
Other languages
Korean (ko)
Other versions
KR920000478B1 (en
Inventor
문성호
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890011091A priority Critical patent/KR920000478B1/en
Publication of KR910005158A publication Critical patent/KR910005158A/en
Application granted granted Critical
Publication of KR920000478B1 publication Critical patent/KR920000478B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
  • Rotational Drive Of Disk (AREA)

Abstract

내용 없음No content

Description

FDD인덱스 보정회로FDD index correction circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 회로도.3 is a circuit diagram of the present invention.

제4도는 본 발명의 실시예에 의한 타이밍도.4 is a timing diagram according to an embodiment of the present invention.

Claims (3)

듀티 사이클 결정을 위한 제1듀티 사이클 결정수단과, SP모터부의 홀센서와 Vcc전원과 연결된 저항(R1)및 상기 제1듀티 사이클 결정수단에 연결되어 불안정한 신호를 받아 시상수에 의해 일정시간 지연된 신호를 발생시키는 제1단안정 멀티바이브레이터(T1)와, 듀티 사이클 결정을 위한 제2듀티 사이클 결정수단과, 상기 제1단안정 멀티바이브레이터(T1)의 출력 및 제2듀티 사이클 결정수단에 연결되어 시상수에 의해 PC시스템이 원하는 클럭 펄스를 발생시키는 제2단안정 멀티바이브레이터(T2)로 구성된 것을 특징으로 FDD인덱스 보성회로.The first duty cycle determination means for duty cycle determination, the resistor R1 connected to the Hall sensor and the Vcc power supply of the SP motor unit, and the first duty cycle determination means are connected to the first duty cycle determination means to receive a signal delayed by a time constant for a predetermined time. Connected to the first single-stable multivibrator T1, the second duty cycle determining means for duty cycle determination, the output of the first single-stable multivibrator T1, and the second duty cycle determining means. And a second single-stable multivibrator (T2) for generating a desired clock pulse by the PC system. 제1항에 있어서, 상기 제1듀티 사이클 결정 수단은 가변저항(VR1) 및 캐패시터(C1)가 직렬로 구성되어 있으며, 상기 가변저항(VR1)과 캐패시터(C1) 연결 사이에서 상기 제1단안정 멀티바이브레이터(T1)와 CR단자로 연결된 것을 특징으로 하는 FDD인덱스 보정회로.The method of claim 1, wherein the first duty cycle determination unit comprises a variable resistor (VR1) and a capacitor (C1) in series, the first stage stability between the variable resistor (VR1) and the capacitor (C1) connection An FDD index correction circuit characterized by being connected to a multivibrator (T1) and a CR terminal. 제1항에 있어서, 상기 제2듀티 사이클 결정 수단은 저항(R2) 및 캐패시터(C2)가 직렬로 구성되어 있으며, 상기 저항(R2)가 캐패시터(C2) 연결사이에서 상기 제2단안정 멀티바이브레이터(T2)의 CR단자로 연결된 것을 특징으로 하는 FDD인덱스 보정회로.The method of claim 1, wherein the second duty cycle determination unit comprises a resistor R2 and a capacitor C2 in series, and the resistor R2 is connected between the capacitor C2 and the second single-stable multivibrator. An FDD index correction circuit characterized in that it is connected to the CR terminal of (T2). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890011091A 1989-08-03 1989-08-03 A circuit for compensating fdd index KR920000478B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890011091A KR920000478B1 (en) 1989-08-03 1989-08-03 A circuit for compensating fdd index

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890011091A KR920000478B1 (en) 1989-08-03 1989-08-03 A circuit for compensating fdd index

Publications (2)

Publication Number Publication Date
KR910005158A true KR910005158A (en) 1991-03-30
KR920000478B1 KR920000478B1 (en) 1992-01-14

Family

ID=19288702

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890011091A KR920000478B1 (en) 1989-08-03 1989-08-03 A circuit for compensating fdd index

Country Status (1)

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KR (1) KR920000478B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BRPI0815029B1 (en) 2007-08-06 2019-01-29 General Cable Tech Corp insulation composition for an electrical cable and process for making an electrical cable having said insulation composition

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KR920000478B1 (en) 1992-01-14

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