KR910003175Y1 - High density multilayer printed circuit board - Google Patents

High density multilayer printed circuit board Download PDF

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Publication number
KR910003175Y1
KR910003175Y1 KR2019900006890U KR900006890U KR910003175Y1 KR 910003175 Y1 KR910003175 Y1 KR 910003175Y1 KR 2019900006890 U KR2019900006890 U KR 2019900006890U KR 900006890 U KR900006890 U KR 900006890U KR 910003175 Y1 KR910003175 Y1 KR 910003175Y1
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South Korea
Prior art keywords
layers
holes
layer
circuit board
printed circuit
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KR2019900006890U
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Korean (ko)
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기요시 구와바라
미끼오 니시하라
가즈히사 쯔노이
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
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Priority claimed from JP1984198910U external-priority patent/JPH023631Y2/ja
Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마 filed Critical 후지쓰 가부시끼가이샤
Priority to KR2019900006890U priority Critical patent/KR910003175Y1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

내용 없음.No content.

Description

고밀도 다층 인쇄 회로기판High Density Multilayer Printed Circuit Board

제1도는 종래의 다층 인쇄 회로기판의 개략 횡단면도.1 is a schematic cross-sectional view of a conventional multilayer printed circuit board.

제2도는 본 고안에 의한 다층 인쇄회로 기판의 일실시예의 개략횡단면도.Figure 2 is a schematic cross-sectional view of one embodiment of a multilayer printed circuit board according to the present invention.

제3도는 본 고안에 의한 다층 인쇄회로 기판의 다른 실시예의 개략 횡단면도.3 is a schematic cross-sectional view of another embodiment of a multilayer printed circuit board according to the present invention.

제4a-4c도는 제3도의 선들 X-X, Y-Y 및 Z-Z를 따라 취한 절단면들을 나타내는 개략 평면도.4A-4C are schematic plan views showing cut planes taken along lines X-X, Y-Y and Z-Z of FIG.

본 고안은 고밀도 다층 인쇄 회로기판에 관한 것으로 특히 다수의 신호층들, 전원층 및 접지층을 갖는 고밀도다층 인쇄회로기판에 관한 것이다.The present invention relates to a high density multilayer printed circuit board, and more particularly, to a high density multilayer printed circuit board having a plurality of signal layers, a power supply layer, and a ground layer.

최근에 전자계산기의 고속화에 발맞춰 LSI등이 실장되는 인쇄 회로기판이 고밀도 또한 다층으로 제조되는것이 요구되어 왔다.In recent years, it has been demanded that printed circuit boards on which LSIs or the like are mounted have been made of high density and multilayer in order to increase the speed of the electronic calculator.

즉, 이전에는 1개의 인쇄 회로기판에서 소수층의 신호층으로 충분하던 것이 10층 이상의 신호층을 필요로한다. 즉, 신호 층수의 증가에 따라서 이에 대응한 전원층과 접지층의 수들이 불가피하게 증가되어야 하기때문에 결국 인쇄 회로기판이 두꺼워져서 좋지 않다.In other words, a signal layer having a small number of layers in one printed circuit board requires more than 10 signal layers. That is, as the number of signal layers increases, the number of power supply layers and ground layers corresponding to the number of signal layers must inevitably increase, resulting in a thick printed circuit board.

종래에는 다수의 전원층과 기타층들에 의해 두꺼운 기판으로서 형성되면 전원층과 기타층들의 랜드들(land)이 각각 하나의 관통공의 도체부에 전기적으로 연결되었다. 이 관통공은 드릴로 형성해야만하며 그에 대응하는다수의 동으로 된 랜드들을 관통하는 하나의 구멍을 뚫어 주어야 하므로 드릴비트의 절삭 표면부에 심한 부하가 가해지므로, 결국 드릴비트의 절삭 표면이 빨리 마모되어 무뎌지는 문제점이 있다.Conventionally, when formed as a thick substrate by a plurality of power supply layers and other layers, lands of the power supply layer and the other layers are each electrically connected to the conductor portion of one through hole. This through hole must be formed with a drill and must drill a hole through the corresponding copper lands, which puts a heavy load on the cutting surface of the drill bit, so that the cutting surface of the drill bit wears out quickly. There is a problem that becomes dull.

본 고안의 목직은 관통공들의 도체부에 연결된 전원층과 다른층들의 랜드들이 수적으로 균등하게 분산되도록 형성된 고밀도 다쏭 인쇄 회로기판을 제공함으로써 상술한 문제점들을 제거하는데 있다.The object of the present invention is to eliminate the above-mentioned problems by providing a high-density dachshund printed circuit board formed so that the lands of the power supply layer and the other layers connected to the conductor portions of the through holes are distributed evenly in number.

본 고안의 다른 목적은 그러한 기판의 제조시에 사용되는 드릴과 같은 공구의 마모가 종래 기술에 의한 기판제조시에 생기는 또다 적은 고밀도 복수층 인쇄 회로기판을 제공하는데 있다.It is another object of the present invention to provide a high density multi-layer printed circuit board in which wear of tools such as drills used in the manufacture of such substrates occurs in the manufacture of substrates according to the prior art.

본 고안에 의하면, 신호층들, 전원층들 및 접지층들과 각 신호층과 전원층과의 사이 각 전원층과 전원층과의사이, 및 각 접지층과 신호층과의 사이에 삽입되어 있는 절연층들과, 신호층들, 전원층들 및 접지층들에 대해서 수지 방향으로 형성되고 랜드를 거쳐서 상기 신호층들 및/또는 전원층들 및1또는 접지층들에 전기직으로연결되어 있는 도체부들과 상기 도체부들간에 균등 분산되어 연결되어 있는 랜드들로 구성되는 고밀도 다층인쇄 회로기판이 제공된다.According to the present invention, the signal layers, the power layers, and the ground layers, and between each signal layer and the power layer, are inserted between each power layer and the power layer, and between each ground layer and the signal layer. Conducting portions formed in the resin direction with respect to the insulating layers, the signal layers, the power layers and the ground layers and electrically connected to the signal layers and / or the power layers and the 1 or ground layers via lands. And a high density multilayer printed circuit board comprising lands that are evenly distributed and connected between the conductor parts.

이하 첨부도면을 참조하여 본원 발멀의 양호한 실시예를 설명하겠다.DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the Valmal application will be described with reference to the accompanying drawings.

우선 본 발명의 실시예를 설명하기 전에 종래 기술에 관해서 설명하겠다.First, prior art will be described before describing embodiments of the present invention.

제1도는 신호층들(C)과 전원층들(B)을 갖는 종래의 다층 인쇄 회로기판의 개략 횡단면도를 나타내고 있다.1 shows a schematic cross-sectional view of a conventional multilayer printed circuit board having signal layers C and power supply layers B. FIG.

제1도에 보인 바와같이 복수의 도체층(1)으로 다층 회로기판을 형성하고 있으며, 각 도체층(1)은 도체 패턴용 절연판(2)위에 형성되며, 랜드(3)을 갖고 있다.As shown in Fig. 1, a multilayer circuit board is formed of a plurality of conductor layers 1, and each conductor layer 1 is formed on an insulating plate 2 for a conductor pattern and has a land 3 thereon.

이 다층 회로기판에서, 신호층(C)과 전원층들(B)이 표면층(A) 아래에서 상호 교호로 적층되어 있다.In this multilayer circuit board, the signal layer (C) and the power supply layers (B) are alternately stacked under the surface layer (A).

도체부(5)를 형성하기 위하여 적층된 층들(1)의 수직 방향으로 구멍들(4)을 뚫고, 이 구멍들(4)을 동으로도금하여 관통공(6)을 형성하므로 신호층들(C)와 전원층들(B)에 형성된 랜드들(3)은 도체부(5)에 전기적으로연결된다.In order to form the conductor part 5, the holes 4 are drilled in the vertical direction of the stacked layers 1, and the holes 4 are plated with copper to form the through holes 6 so that the signal layers ( Lands 3 formed in C and the power layers B are electrically connected to the conductor portion 5.

여기서, 각 전원층(B)의 전원이 동종인 경우, 그 전원용으로 단 하나의 관통공(61)만을 설비하여 모든랜드들(31)을 관통공(61)의 도체부(5)에 전기적으로 연결하도록 되어 있다. 이로 인해서 각 전원층(B)을 연결하는 관통공(61)의 도체패턴 또는 랜드를 완전히 동일하게 제조할 수 있는 이점이 있다.Here, when the power source of each power source layer B is the same type, only one through hole 6 1 is provided for the power source and all the lands 3 1 are connected to the conductor portion 5 of the through hole 6 1 . It is intended to be electrically connected. Therefore, there is an advantage that the conductor pattern or land of the through hole 6 1 connecting each power source layer B can be manufactured to be exactly the same.

그러나, 모든 전원층(B)의 랜드들(31)이 관통공(61)에 집중되어 있기 때문에 랜드들(31)이외에도 다수의 절연판(2)은 드릴등으로 뚫어 관통공(61)를 형성해야만 한다.However, since the lands 3 1 of all the power supply layers B are concentrated in the through holes 6 1 , the plurality of insulating plates 2 in addition to the lands 3 1 are drilled to drill through holes 6 1. ) Must be formed.

그로 인해서 드릴에 큰 부하가 가해져서 관통공내에서 드릴 비트가 파손되거나 구멍이 구부러지게 뚫리는문제들이 발생된다.As a result, a large load is applied to the drill, causing problems in that the drill bit is broken or the hole is bent in the through hole.

더우기 신호층들의 층수를 더욱 증가시킬 경우에는 신호층들(C)은 상호 간섭을 일으켜 잡음 발생이 증가된다.Furthermore, when the number of layers of the signal layers is further increased, the signal layers C cause mutual interference to increase noise generation.

이러한 잡음 발생을 방지하기 위해서 신호 층들(C)사이에 접지층들을 배치하고 있다.In order to prevent the occurrence of noise, ground layers are disposed between the signal layers C.

이와같은 구성에서는 수층마다 접지층을 배치하여 그 접지층을 완전히 공통화시킬 수 있으므로 전술한 전원층과 마찬가지로 랜드들은 집중시키는 것이 가능하게 된다.In such a configuration, the ground layer can be arranged in several layers so that the ground layer can be made common, so that lands can be concentrated like the power layer described above.

그러나, 접지층들을 추가하여 잡음발생을 감소시킬 수는 있지만 전술한 바와같이 신호층들(C)을 뚫을때에드릴에 심한 부하가 가해지는 문제점을 가중시킨다.However, it is possible to reduce noise generation by adding ground layers, but as described above, it adds to the problem that a heavy load is applied to the drill when drilling the signal layers (C).

제2도는 본 고안에 의한 인쇄 회로기판의 일실시예의 개략 횡단면도를 나타내고 있다.2 is a schematic cross-sectional view of an embodiment of a printed circuit board according to the present invention.

제2도에 나타낸 바와같이, 다층 인쇄기판은 신호층들(C)과 예를들어 4V의 동일 전원을 갖는 전원층들(B,B‥‥‥ B6)을 갖고 있다. 신호층들(C)과 전원층들(B, B1,‥‥‥‥B6)은 교호로 적층되어 패키지화된 다층 인쇄회로기판을 형성하고 있다.As shown in FIG. 2, the multilayer printed circuit board has signal layers C and power supply layers B, B ... B 6 having the same power supply of 4V, for example. The signal layers C and the power layers B, B 1 ,... B 6 are alternately stacked to form a packaged multilayer printed circuit board.

여기서는 전원공급용으코 복수개 즉, 3개의 관통공(6a. 6b, 6c)이 제공되어 있다.Here, a plurality of through holes 6a, 6b, 6c are provided for power supply.

이 실시예에서는 최상위(또는 제1)전원층(B)의 랜드들(3a, 3b, 3c)은 각각 관통공(6a, 6b, 6c)을 형성하고있는 도체부들(5a. 5b, 5c)에 전기적으로 연결되어 있고, 제2전원층(B1)의 랜드(3a) 관통공(6a)을 형성하고있는 도체부(5a)에 전기직으로 연결되어 있으며, 제3전원층(B2)의 랜드(3b)는 관통공(6b)을 형성하고 있는도체부(5b)에 전기적으로 연결되어 있고, 또 제4전원층(B3)의 랜드(3c)는 관통공(6c)를 형성하고 있는도체부(5c)에 전기적으로 연결되어 있다. 또 전원층들(B4, B5, B6)의 랜드들 역시 도체부들(5a, 5b, 5c)에제각기 전기적으로 연결되어 있다.In this embodiment, the lands 3a, 3b, 3c of the uppermost (or first) power source layer B are formed in the conductor portions 5a. 5b, 5c, which form the through holes 6a, 6b, 6c, respectively. It is electrically connected to the conductor portion 5a which is electrically connected, and forms the through hole 6a of the land 3a of the second power source layer B 1 , and is connected to the conductor portion 5a of the third power source layer B2. 3b is electrically connected to the conductor portion 5b forming the through hole 6b, and the land portion 3c of the fourth power source layer B3 forms the conductor portion 6c forming the through hole 6c. Is electrically connected to 5c). In addition, lands of the power layers B 4 , B 5 , and B 6 are also electrically connected to the conductor parts 5a, 5b, and 5c, respectively.

결국 모든 랜드들은 3개의 관통공들에 균등하게 분산되는 식으로 도체부들에 전기적으로 연결되어 있다.Eventually all lands are electrically connected to the conductor parts in such a way that they are evenly distributed in the three through holes.

따라서, 본 고안에 의한 인쇄 회로기판인 본 실시예에서는 각 관통공에 연결된 랜드들의 수가 종래의 방법으로 연결된 수의 1/3로 감소된다.Therefore, in this embodiment, which is a printed circuit board according to the present invention, the number of lands connected to each through hole is reduced to 1/3 of the number connected by the conventional method.

제3도는 본 고안에 의한 인쇄 회로기판의 다른 실시예로서 접지층이 배치되었을 경우의 다층 배선기판의개략 횡단면도를 나타내며, 제4a내지 4c도는 제3도의 선들(X-X, Y-Y, Z-Z)에 따라서 취한 절단면들을나타내는 부분 개략 평면도들이다.3 is a schematic cross-sectional view of a multilayer wiring board when a ground layer is disposed as another embodiment of a printed circuit board according to the present invention, and FIGS. 4a to 4c are taken along the lines XX, YY, and ZZ of FIG. Partial schematic plan views showing the cut planes.

제3 및 4도에 나타낸 바와같이, 접지층들(G, G‥‥‥‥G,.)는 신호층들(C)사이에 배치되어 있다. 본 실시예에서는 신호층들(C)과 전원층들(V1, V2)의 연결용 관통공(도시안됨) 이외에도 접지층들의 연결용 관통공들(7a, 7b, 7c)이 제공된 경우를 설명한다.As shown in Figs. 3 and 4, the ground layers G, G, ..., G, ... are disposed between the signal layers C. As shown in Figs. In the present exemplary embodiment, in addition to the through holes (not shown) for connecting the signal layers C and the power layers V1 and V2, the through holes 7a, 7b, and 7c for connecting the ground layers are provided. .

본 고안의 이 실시예에서는 최상위 접지층(G)의 랜드들(8a, 8b, 8c)은 제4a도에 구체적으로 나타낸 바와같이 관통공들(7a, 7b, 7c)를 형성하고 있는 도체부들(5a, 5b, 5c)에 전기적으로 연결되어 있다.In this embodiment of the present invention, the lands 8a, 8b, 8c of the uppermost ground layer G have conductor parts (7a, 7b, 7c) which form through holes 7a, 7b, 7c, as shown in FIG. 5a, 5b, 5c).

제3, 4b 및 4c도에서 볼 수 있는 바와같이 접지층(G1)의 랜드(8b)는 관통공(7b)를 형성하고 있는도체부(5b)에 전기적으로 연결되어 있으며, 또한 접지층(G2)와 랜드들(8a, 8c)은 관통공들(7a, 7c)을 형성하고 있는 도체부분을(5a, 5c)에 전기적으로 연결되어 있다.As can be seen in FIGS. 3, 4b and 4c, the land 8b of the ground layer G 1 is electrically connected to the conductor portion 5b forming the through hole 7b. G 2 ) and lands 8a and 8c are electrically connected to conductor portions 5a and 5c forming through holes 7a and 7c.

또, 접지층(G3, G4‥‥‥‥G5)의 랜드들도 각 도체부들에 균등하게 분산되어 연결되어 있다.관통공들의 수와 랜드들의 그룹화는 상기 실시예로 정해진 것이 아니고, 경우에 따라서 변경될 수도 있다.In addition, ground layers (G 3, G 4 ‥‥‥‥ G 5) lands are also connected to the conductor portions are evenly distributed, grouped by the number of the through-hole and the land of the not be committed to the above embodiment, It may be changed in some cases.

Claims (3)

복수의 신호층(C), 복수의 전원층(B), 복수의 접지층(G)을 포함하는 특수의 도체층(1), 인접하는 상기신호층들과 상기 전원층들과의 사이, 인접하는 상기 전원층들과 상기 접지층들과의 사이, 및 인접하는 상기접지층들과 상기 신호층들과의 사이에 배치되고 상기 복수의 도체층과 석층배치되어 있는 복수의 절연층(2),상기 적층된 복수의 도체층(1)과 상기 복수의 절연층(2)을 수직 관통하는 구멍들(4) 각각에 도체부(5)가 형성되어 있는 복수의 관통공(6)으로 구성되는 다층 인쇄 회로기판에 있어서, 상기 복수의 전원층(B)과 관련되는복수의 제1관통공(6a, 6b, 6c), 상기 복수의 접지층(G)과 관련되는 복수의 제2관통공(7a, 7b, 7c), 상기 복수의 제1관통공의 상기 도체부(제2도 5a, 5b, 5c)에 상기 전원층을 선택적으로 연결하기 위해 상기 전원층에 선택적으로 형성되는 도전 랜드들(3a,3b,3c), 상기 복수의 제2관통공의 상기 도체부(제3도 5a,5b,5c)에상기 접지층을 선택적으로 연결하기 위해 상기 접지층에 선택적으로 형성되는 도전 랜드들(8a, 8b, 8c)을 포함하고 있어, 상기 전원층과 접지층과 관렬된 도전 랜드들이 상기 전원층과 접지층과 관련된 제1 및 제2관통공들에 대해 상기 인쇄 회로기판을 통해 횡방향으로 균등하게 분산되는 것이 특징인 고밀도 복수층 인쇄 회로기판.Special conductor layer 1 comprising a plurality of signal layers C, a plurality of power layers B, and a plurality of ground layers G, between adjacent signal layers and the power layers, adjacent A plurality of insulating layers 2 disposed between the power supply layers and the ground layers, and between the adjacent ground layers and the signal layers and disposed with the plurality of conductor layers and stone layers, Multi-layer consisting of a plurality of through-holes 6 in which a conductor portion 5 is formed in each of the plurality of conductor layers 1 and the holes 4 vertically penetrating the plurality of insulating layers 2. In the printed circuit board, a plurality of first through holes 6a, 6b, 6c associated with the plurality of power supply layers B, and a plurality of second through holes 7a associated with the plurality of ground layers G. And 7b, 7c), which are selectively formed in the power supply layer to selectively connect the power supply layer to the conductor portion (2 FIGS. 5A, 5B, 5C) of the plurality of first through holes. All lands 3a, 3b and 3c are selectively formed in the ground layer to selectively connect the ground layer to the conductor portion (3rd FIGS. 5A, 5B, 5C) of the plurality of second through holes. Conductive lands 8a, 8b, 8c, wherein the conductive lands in contact with the power supply layer and the ground layer connect the printed circuit board to the first and second through holes associated with the power supply layer and the ground layer. A high density multilayer printed circuit board, characterized in that it is evenly distributed in the transverse direction through. 제1항에서, 상기 전원층들의 상기 랜드들은 상기 3개의 관통공들(6a, 6b, 6c)의 상기 도체부들(5a, 5b,5c) 가운데에 균일하게 분산되는 것이 특징인 고밀도 복수층 인쇄 회로기판.2. The high density multilayer printed circuit of claim 1, wherein the lands of the power supply layers are uniformly distributed among the conductor portions 5a, 5b, 5c of the three through holes 6a, 6b, 6c. Board. 제1항에서, 상기 접지층들의 상기 랜드들은 상기 3개의 관통공들(7a, 7b, 7c)을 형성하는 도체부들(5a,5b, 5c)가운데에 균일하게 분포되는 것이 특징인 고밀도 복수층 인쇄 회로기판.2. The high density multilayer printing of claim 1, wherein the lands of the ground layers are uniformly distributed among the conductor portions 5a, 5b, and 5c forming the three through holes 7a, 7b, and 7c. Circuit board.
KR2019900006890U 1984-12-28 1990-05-22 High density multilayer printed circuit board KR910003175Y1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745520B1 (en) * 2006-01-20 2007-08-02 삼성전기주식회사 Multi-layered printed circuit board and the manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745520B1 (en) * 2006-01-20 2007-08-02 삼성전기주식회사 Multi-layered printed circuit board and the manufacturing method thereof

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