KR900013782A - Beat de-interleave circuit for muse voice reception - Google Patents

Beat de-interleave circuit for muse voice reception Download PDF

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Publication number
KR900013782A
KR900013782A KR1019890002318A KR890002318A KR900013782A KR 900013782 A KR900013782 A KR 900013782A KR 1019890002318 A KR1019890002318 A KR 1019890002318A KR 890002318 A KR890002318 A KR 890002318A KR 900013782 A KR900013782 A KR 900013782A
Authority
KR
South Korea
Prior art keywords
buffers
beat
interleave circuit
address
voice reception
Prior art date
Application number
KR1019890002318A
Other languages
Korean (ko)
Other versions
KR920004252B1 (en
Inventor
전지용
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019890002318A priority Critical patent/KR920004252B1/en
Publication of KR900013782A publication Critical patent/KR900013782A/en
Application granted granted Critical
Publication of KR920004252B1 publication Critical patent/KR920004252B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Error Detection And Correction (AREA)

Abstract

내용 없음No content

Description

뮤즈 음성수신용 비트 디-인터리브 회로Beat de-interleave circuit for muse voice reception

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명 회로의 구성도.1 is a block diagram of a circuit of the present invention.

제2도는 제1도의 버퍼메모리 입출력 매트릭스.2 is a buffer memory input / output matrix of FIG.

Claims (1)

고정세 텔레비젼의 음성수신용 비트 디-인터리브회로에 있어서, 기입어드레스와 독출 어드레스를 발생시키는 발생시키는 어드레스 발생기(10)와, 입력신호(DAAT IN)와 기입어드레스를 입력으로 하는 버퍼(20, 22)와 독출 어드레스를 입력으로 하는 버퍼(21, 23)와 버퍼(20-23)의 출력 어드레스를 인가 받아 버퍼(20, 22)의 데이터 출력을 기입 및 독출하는 버퍼메모리(30, 31)와 버퍼메모리(36, 31)의 독출 신호를 출력하는 멀티플렉서(40) 포함하여 구성하는 것을 특징으로 하는 뮤즈 음성수신용 디-인터리브회로.In a bit de-interleave circuit for audio reception of high-definition television, an address generator 10 for generating a write address and a read address, and a buffer 20, 22 for inputting the input signal DAAT IN and the write address. Buffers 30 and 31 that write and read data outputs of the buffers 20 and 22 by receiving the buffers 21 and 23 that input the read address and the output addresses of the buffers 20 and 23. And a multiplexer (40) for outputting a read signal of the buffer memory (36, 31). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890002318A 1989-02-27 1989-02-27 Bit de-interleave circuit KR920004252B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890002318A KR920004252B1 (en) 1989-02-27 1989-02-27 Bit de-interleave circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890002318A KR920004252B1 (en) 1989-02-27 1989-02-27 Bit de-interleave circuit

Publications (2)

Publication Number Publication Date
KR900013782A true KR900013782A (en) 1990-09-06
KR920004252B1 KR920004252B1 (en) 1992-05-30

Family

ID=19284088

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890002318A KR920004252B1 (en) 1989-02-27 1989-02-27 Bit de-interleave circuit

Country Status (1)

Country Link
KR (1) KR920004252B1 (en)

Also Published As

Publication number Publication date
KR920004252B1 (en) 1992-05-30

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