KR900010298Y1 - Horizontal drive circuit for liquid crystal monitor - Google Patents
Horizontal drive circuit for liquid crystal monitor Download PDFInfo
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- KR900010298Y1 KR900010298Y1 KR2019870009055U KR870009055U KR900010298Y1 KR 900010298 Y1 KR900010298 Y1 KR 900010298Y1 KR 2019870009055 U KR2019870009055 U KR 2019870009055U KR 870009055 U KR870009055 U KR 870009055U KR 900010298 Y1 KR900010298 Y1 KR 900010298Y1
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- liquid crystal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 액정콘트롤러와 액정모듈 회로도.1 is a circuit diagram of a conventional liquid crystal controller and a liquid crystal module.
제2도는 본 고안에 따른 회로도.2 is a circuit diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
CNT : 카운터 RI-RN : 저항CNT: Counter RI-RN: Resistance
SWI-SWN : 딥스위스 EXI-EXN : 익스클루시브오아게이트SWI-SWN: Deep Swiss EXI-EXN: Exclusive Oagate
AN : 앤드게이트AN: Andgate
본 고안은 도트 매트릭스(DOT MATRIX)형 액정(LCD; LIUID CRYSTAL DISPLAY) 판넬(PANEL)을 사용한 액정모니터의 구동회로에 관한 것으로, 특히 수평구동회로의 채널(CHANNEL)수에 상관없이 액정컨트롤러를 선택하여 제어할 수 있도록 하는 칩 인에이블 발생회로에 관한 것이다.The present invention relates to a driving circuit of a liquid crystal monitor using a dot matrix (LCD) liquid crystal display panel (PANEL), and in particular, selects a liquid crystal controller irrespective of the number of channels of a horizontal driving circuit. It relates to a chip enable generation circuit that can be controlled by.
일반적인 도트매트릭스 액정 판판을 사용한 액정모니터 구동회로는 제1도와 같다.A liquid crystal monitor driving circuit using a general dot matrix liquid crystal plate is shown in FIG.
제1도는 프로그램을 수행하여 입력되는 데이타를 처리하는 중앙처리장치(1)와, 영상데이타를 내장할 수 있는 비데오 메모리(3)와, 소정의 이미지를 표시할 수 있는 도트매트릭스형 액정판넬(12)와, 상기 도트매트릭스형 액정판넬(12)의 액정을 상기 중앙처리장치(1)의 제어와 비데오메모리(3)의 출력에 의해 구동하도록 제어하는 콘트롤러 회로(2)와, 상기 도트매트릭스형 액정 판넬(12)에 수평신호를 액정 콘트롤러회로(2)에서 발생되는 라인입력펄스신호(LP)와 프레임신호(FM) 직동깊및 액정구동용교류신호(FB)를 받아 드라이브하여 공급하는 수직드라이버회로(5)와, 상기 도트매트릭스형 액정 판넬(12)에 수평신호를 드라이브하여 공급하는 수평 드라이버회로(6-11)와, 상기 액정 콘트롤러 회로(2)의 클럭(CK)과 플레임(FM)신호를 받아 상기 수평드라이버회로(6-11)의 칩인에이블 신호를 발생하는 수평드라이버 칩 인에이블 신호 발생회로(4)로 구성하여 왔었다.FIG. 1 shows a central processing unit 1 which executes a program to process input data, a video memory 3 capable of embedding image data, and a dot matrix liquid crystal panel 12 capable of displaying a predetermined image. ), A controller circuit 2 for controlling the liquid crystal of the dot matrix liquid crystal panel 12 to be driven by the control of the central processing unit 1 and the output of the video memory 3, and the dot matrix liquid crystal. Vertical driver circuit for driving the horizontal signal to the panel 12 by receiving the line input pulse signal LP generated from the liquid crystal controller circuit 2 and the frame signal FM direct movement depth and the liquid crystal drive AC signal FB. (5), a horizontal driver circuit 6-11 for driving and supplying a horizontal signal to the dot matrix liquid crystal panel 12, and a clock (CK) and flame (FM) signal of the liquid crystal controller circuit 2; The horizontal driver circuit (6-11) It came to consist of an enable signal generating circuit 4, the horizontal driver chip for generating the chip enable signal.
액정 콘트롤러회로(2)에서 오는 데이타 수평드라이버 회로(6-11)에 전달되면 수평드라이버 회로(6-11)의 쉬프트 클럭펄스(CLP)신호에 의해 쉬프트 되는데 최초 수평드라이버 회로에 데이타가 모두 채워질 동안 나머지 다른 수평드라이버 회로는 동작할 필요가 없게 된다.When the data from the liquid crystal controller circuit 2 is transferred to the horizontal driver circuit 6-11, it is shifted by the shift clock pulse (CLP) signal of the horizontal driver circuit 6-11, while all the data is filled in the first horizontal driver circuit. The other horizontal driver circuits do not need to operate.
따라서 수평드라이버회로의 채널수와 한번에 들어오는데 이타수에 따라 일정한 CLP마다 칩인에이블 신호를 발생시켜야 한다. (예를 들면 80채널웨 드라이버에 한번이 4비트씩 병렬로 들어오면 20개의 CLP마다 한개의 칩 인에이블 신호가 발생된다).Therefore, the chip enable signal should be generated for every constant CLP according to the number of channels and the number of channels in the horizontal driver circuit. (For example, one 4-bit parallel to an 80-channel wew driver generates one chip enable signal for every 20 CLPs).
상기한 바와 같이 종래는 액정 모니터의 수평드라이버의 채널수에 따른 해당 수평 칩인에이블 신호발생회로만을 완전히 고정(FIX)되어 사용하여 왔었다. 이에 따라 채널수 변화에 따라 액정 콘트롤러 회로(2)의 선택에 상당한 주의를 요하는 문제점이 있었다.As described above, conventionally, only the horizontal chip enable signal generation circuit according to the number of channels of the horizontal driver of the liquid crystal monitor has been completely fixed (FIX) and used. Accordingly, there has been a problem that requires considerable attention to the selection of the liquid crystal controller circuit 2 in accordance with the change in the number of channels.
따라서 본 고안의 목적은 액정모니터의 수평드라이버 회로의 칩인에이블 신호를 딥 스위치에 의해 프로그램 어블하게 지정할 수 있도록 하여 수평 드라이버 회로의 채널수에 구애됨이 없이 구동할 수 있는 회로를 제공함에 있다.Accordingly, an object of the present invention is to provide a circuit capable of designating a chip enable signal of a horizontal driver circuit of a liquid crystal monitor by a dip switch to be driven regardless of the number of channels of a horizontal driver circuit.
이하 본 고안을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 회로도로서, CNT는 카운터, RI-RN은 저항, SWI-SWN은 딥 스위치, EXI-EXN은 익스클루시브오아게이트, AN은 앤드게이트이며, 상기 카운터(CNT)의 클리어단(CLR)에 제1도의 액정 콘트롤러회로 프레임신호(FM)을 입력하고 수평드라이버의 쉬프트 클럭펄스(CLP)를 클럭(CLK)단으로 입력하여 상기 카운터(CNT)의 각 출력단(Q1-QN)을 익스클루시브 오아 게이트(EXI-EXN)에 입력하고 전원(VCC)으로 부터 연결된 저항(R1-RN)과 접지와 연결된 딥스위치(SW1-SWN)를 익스클루시브오아게이트(EXI-EXN)의 각단에 입력하여 상기 익스클로시브오아게이트(EXI-EXN)를 앤드게이트(AN)로 입력되어 칩인에이블(CE)신호를 발생하도록 구성된다.2 is a circuit diagram according to the present invention, wherein CNT is a counter, RI-RN is a resistor, SWI-SWN is a dip switch, EXI-EXN is an exclusive ogate, AN is an AND gate, and the counter CNT is cleared. The liquid crystal controller circuit frame signal FM of FIG. 1 is input to the stage CLR, and the shift clock pulse CLP of the horizontal driver is input to the clock CLK stage, thereby outputting each output terminal Q1-QN of the counter CNT. To the exclusive ora gate (EXI-EXN) and the resistor (R1-RN) connected from the power supply (VCC) and the dip switch (SW1-SWN) connected to the ground of the exclusive oragate (EXI-EXN). It is configured to input the end of the exclusive or gate (EXI-EXN) to the AND gate (AN) to generate a chip enable (CE) signal.
따라서 본 고안의 구체적 일실시예를 제2도를 참조하여 상세히 설명한다.Therefore, a specific embodiment of the present invention will be described in detail with reference to FIG.
제1도 액정 콘트롤러 회로(2)로부터 프레임신호(FM)과 수평드라이버 쉬프트 클럭펄스신호(CLP)를 카운터(CNT)의 클리어단(CLR)으로 받아 소정의 N비트로 카우트하면 (N비트값은 채널수와 한번에 들어오는 데이타를 고려하여 결정함)상기 카운터(CNT)의 출력(QI-QN)을 익스클루시오아게이트(EXI-EXN)의 제1입력단(2AI-2AN)을 통해 입력되는데 딥스위치(SWI-SWN)조작에 따라 원하는 값을 설정하여 카운터(CNT)의 출력(QI-QN)과 동시에 제2입력단(2BI-2BN)을 통해 입력된다. 즉 딥스위치(SWI-SWN)중 온되는 스위치단의 전위는 "로우"가 되므로 익스클루시오아게이트(EXI-EXN)의 상태도 또한 변환되므로 카운터(CNT)의 출력(QI-QN)과 상기 딥스위치(SWI-SWN)의 설정값에 따라 제1, 2입력단(2AI-2AN,2BI-2BN)이 서로 다를때 "하이"가 출력되어 앤드게이트(3)을 통해 출력시키면 1-2사이의 원하는 수평 드라이버의 쉬프트 클럭펄스신호(CLP)의 수에 한번씩 신호를 발생시킬 수 있다. 그리고 프레임신호(FM)로 카운터(CNT)를 클리어시키면 프레임신호(FM)의 기점으로 부터 원하는 CLP의 숫자마다 한번씩 신호를 발생시킨다.When the frame signal FM and the horizontal driver shift clock pulse signal CLP are received from the liquid crystal controller circuit 2 in the clear terminal CLR of the counter CNT and counted to a predetermined N bit, The output QI-QN of the counter CNT is input through the first input terminal 2AI-2AN of the EXO-EXN. A desired value is set according to the operation of SWI-SWN, and is input through the second input terminal 2BI-2BN simultaneously with the output QI-QN of the counter CNT. That is, since the potential of the switch stage turned on during the dip switch SWI-SWN becomes "low", the state of the exclusive gate EXI-EXN is also converted, so that the output QI-QN and the dips of the counter CNT are changed. When the first and second input terminals 2AI-2AN and 2BI-2BN are different from each other according to the setting value of the position SWI-SWN, "high" is outputted and outputted through the AND gate 3 to the desired value between 1-2. The signal may be generated once for the number of shift clock pulse signals CLP of the horizontal driver. When the counter CNT is cleared with the frame signal FM, a signal is generated once for each desired number of CLPs from the starting point of the frame signal FM.
상술한 바와같이 수평드라이브 회로의 채널수나 한번에 나가는 데이타의 수에 상관없이 딥스위치(SWI-SWN)를 설정하여 적절한 칩 인에이블 신호를 만들어 줌으로서 기존의 콘트롤러 집적회로와 드라이버 집적회로사이의 선택도를 넓힐 수 있다.As described above, regardless of the number of channels of the horizontal drive circuit or the number of outgoing data at once, the dip switch (SWI-SWN) is set to generate an appropriate chip enable signal, thereby selecting the existing controller integrated circuit and the driver integrated circuit. You can widen it.
즉 액정 모티너와 같이 도트 매트릭스형의 표시소자(EL 및 PLASMA등)에서도 수평 드라이버 회로의 채널이 다양함으로서 (32채널,64채널등)동일 회로로서 드라이브 회로의 채널수에 상관없이 액정 모니터를 구동할 수 있는 이점이 있다.In other words, even in dot matrix type display devices (EL and PLASMA, etc.) like the liquid crystal monitors, the channel of the horizontal driver circuit is varied (32 channels, 64 channels, etc.). There is an advantage to this.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870009055U KR900010298Y1 (en) | 1987-06-05 | 1987-06-05 | Horizontal drive circuit for liquid crystal monitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870009055U KR900010298Y1 (en) | 1987-06-05 | 1987-06-05 | Horizontal drive circuit for liquid crystal monitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890001721U KR890001721U (en) | 1989-03-20 |
| KR900010298Y1 true KR900010298Y1 (en) | 1990-11-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019870009055U KR900010298Y1 (en) | 1987-06-05 | 1987-06-05 | Horizontal drive circuit for liquid crystal monitor |
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| Country | Link |
|---|---|
| KR (1) | KR900010298Y1 (en) |
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1987
- 1987-06-05 KR KR2019870009055U patent/KR900010298Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR890001721U (en) | 1989-03-20 |
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