KR900008858B1 - Image sign apparatus by line buffer - Google Patents

Abstract

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Description

Image Coding Device Using Line Buffer

1 is a conventional object recognition block diagram using a computer.

2 is a circuit diagram of the present invention.

3 is a detailed circuit diagram of FIG. 2 showing an embodiment of the present invention.

4 shows a 2x2 window in 256x256 bit size.

5 is the pattern of the information code

* Explanation of symbols for main parts of the drawings

1, 2: Line buffer 3: D flip-flop

4: binary counter for bit address 5: binary counter for lie address

6: D flip-flop array 7: RPOM

8: Address counter for information code recording 9: SRAM for information code recording

The present invention relates to an image encoding apparatus using a lie buffer, and more particularly, to an image encoding apparatus using a line buffer for obtaining run-length poles having shape information of an object in an image recognition apparatus using a computer. It is about.

In general, in the field of image recognition in which a computer is used to recognize an object, various pieces of information (eg, size, shape, or color) of the object are necessary information for recognizing the object.

In the conventional image processing apparatus, as shown in FIG. 1, in order to obtain the above-mentioned information, the image is digitalized, a black-and-white binary image is stored in a memory, and the computer and the central processing unit use the software information of the object. Calculate

That is, the part which greatly affects the overall processing time is the software part which performs image processing, which is determined by the computing power of the central processing unit.

However, the image processing method related to the conventional software as described above has the following problems.

First, the processing by software is limited by the processing speed. Therefore, the application is limited to machine tools or robots that require real-time image processing.

Second, the Run-Lenght encoder does not have much meaning in itself because it simply finds the length of the information, and the size of the object requires software operation again to obtain the information.

Third, since the relationship with neighboring information is not known at all, the time required for calculation becomes long.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and reduces the time to near real time by hardware information processing, and obtains the correlation with information neighboring itself from the obtained information. An object of the present invention is to provide an image encoding apparatus using a line buffer.

In order to achieve the above object, the present invention provides two line buffers using SRAM, a bit address counter and a line address counter of binary image data, a D flip-flop array for a 2x2 window, and reference. A video encoding apparatus using a line buffer configured to include a PROM storing a pattern of information, an address code recording address counter, and an extracted SRAM for information code recording.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of the present invention, where (1, 2) is a 256 × 1 bit memory for line buffer, (3) a D flip-flop for switch circuit, (4) a binary counter for bit address, and (5) Binary counter for line address, (6) D flip-flop array for 2 x 2 windows, (7) PROM for information pattern recording, (8) address counter for information code recording, (9) for information code recording SRAM.

A preferred embodiment of the present invention having the configuration as described above will be described in detail with reference to the detailed circuit diagram of FIG.

The binarized image data is stored in the line buffers 1 and 2 in series, one bit for each line. At this time, the selection of the line buffer is initially selected as the line buffer 1, and all the bits of one line are input and a carry is generated by the bit counter 4 that counts the lines, thereby switching the line buffer. The line buffer 2 is selected by the state reversal of the switch D flip-flop 3.

)에는 이버터(IN1)에 의해 반전 된 로우레벨 신호가 인가되어 기입산태가 되고, 라인버퍼(2)의 단자(R/

)에는 하이레벨 신호가 인가되어 독출상태가 된다.That is, when the output signal of the D flip-flop 3 is high level, the terminal R / of the line buffer 1

) Is applied to the low-level signal inverted by the inverter IN1 to become a write calculation, and the terminal R / of the line buffer 2 is applied.

A high level signal is applied to the read state.

At this time, the output signal of the D flip-flop 3 is toggled, and this toggle is performed when the line address (the 8-bit counter here, every 256th clock) is the last address.

TABLE 1

)가 반전되어 독출상태가 되므로 라인 i의 영상정보를 출력하고, 라인 버퍼(2)는 기입상태가 되므로 라인 i+1의 영상정보를 기록하게 된다.In the above Table 1, if the line address is the current line i, the line buffer 1 writes the image information of the line i in the write state, and the line buffer 2 outputs the image information of the line i-1 in the read state. If the bit address is m, the line address is increased by 1 before the next clock. At this time, the terminal R / of the line buffer 1

) Is inverted to become a read state, so that the image information of the line i is output, and the line buffer 2 is in the write state, so that the image information of the line i + 1 is recorded.

The binarized image data is inputted to the D flip-flop 61, and the image data previously input to the line buffers 1 and 2 is inputted to the D flip-flop 63 so that the D flip-flop array 6 is 2 ×. 2 Form a window.

As shown in FIG. 4, the 2x2 window forms a window immediately before the current 2x2 window to assist in understanding.

The form of the information code is retrieved by the information pattern recording PROM 7 by inputting 2x2 window data and information fed back the output state of the current branch itself. At this time, the patterns of the information codes as shown in Fig. 5 are already recorded in the corresponding addresses in the PROM 7.

In the present application, only RUN such as START, LAST, JOINT, SPLIT, etc. are arbitrarily given as an example. Depending on the program, it is possible to define a wider variety of modified runs.

The PROM 7 has a code value designated for various predefined runs as shown in FIG.

For example, START RUN can be arbitrarily defined as “f _H ” and LAST RUN as “8 _H ”.

Here, the subscript "H" stands for SMS hexadecimal.

)에는 시스템 클럭이 인가된다. 따라서, 매 2×2윈도우에 의한 런의 발견 및 그 해당 코드값은 현재의 2×2윈도우를 영상신호 및 이전에 발견된 런의 종류에 의해서 결정되어질 수 있다.(본원에서는 런의 종류 지정을 특별히 정하지 않았다.)이를 제6도에 도시한 "A"글자의 화면을 예를 들어 설명한다.The address A _{0 to} A ₃ of the PROM 7 is supplied with the image signal of a 2 × 2 window of the D flip-flop array 6 under investigation, and the addresses A _{4 to} A ₇ are previously found. The code value of the run is applied and the output enable terminal (

Is applied to the system clock. Therefore, the discovery of a run by every 2x2 window and its corresponding code value can be determined by the video signal of the current 2x2 window and the type of the run found previously. It is not specifically determined.) This is described by taking the screen of letter “A” shown in FIG. 6 as an example.

It is assumed that there is image information "A" on a screen having a vertical X horizontal 11 x 12.

It is also assumed that the position of the 2 × 2 window currently in progress is {(0,1), (4,5)}. Here, (0, 1) represents line 0 and line 1, and (4, 5) represents bit 4 and bit 5. This is shown in Table 2 below

TABLE 2

to be.

This corresponds to the START RUN shown in FIG. Therefore, the START RUN code (for example, "F") and the like which are pre-recorded at the addresses A0 to A7 = 00010000 of the PROM 7 are output to the PROM 7.

When the position of the 2x2 window is moved to {(0,1), (5,6)} by the next clock, it becomes the address (A _{0 to} A ₇ = 0011 1111) of the PROM 7, Since it is not the corresponding run of START RUN as shown, the output of the PROM 7 is " 0 ".

Here, 0011 of A _{0 to} A ₃ is a value based on a video signal of a window, and 1111 of A _{4 to} A ₇ is a value of "F" by outputting a code value of a previous run.

Next, when the position of the window is moved to {(0,1), (6,7)} again, as shown in FIG. 5 of the door as shown in the address (A _{0 to} A ₇ = 0011 0000) of the PROM 7 Since it is not the corresponding run of START RUN, the output of PROM 7 becomes "0".

Similarly, the next window is {(0,1), (7,8)}, which is the same as the address (A _{0 to} A ₇ = 00100000) of the PROM 7 and corresponds to START RUN as shown in FIG. The output of (7) becomes 'F', and this output value is also recorded by D0.

Next, no run is detected any more for line (0, 1).

Therefore, " F " and " F " are recorded in the code memory 91 of the information code recording SRAM 9, " 1 " of (0, 1) is recorded in the line address memory 93, and the bit address In the memory 93, "5" of (4,5) and "7" of (6,7) are recorded.

As a result, (F, 1,5) and (F, 1,7) are sequentially recorded in the SRAMT 9 for information code recording of the overall system, so that the START RUN (F code) of the first line is 7 to 7 It can be recorded to continue.

In this way, when all lines are sequentially coded, the memory of the entire system has coded image information (type of run, line number, bit position number) of screen information "A". Thereafter, the computer can process the above information.

That is, if the data format of the 2x2 window matches the type stored in the PROM 7, the output synchronized with the clock signal is SRAM for writing the code through the output terminals D _{0 to} D ₃ of the PROM 7. The bit address and line address are stored in the SRAMs 92 and 93, respectively.

Further, if an address increase pulse synchronized with the clock is output through the AND gate AN1 according to the output D0 of the information pattern recording PROM 7 indicating that a specific information code is generated, the address counter 8 accordingly The address of the information code recording SRAM 9 is increased.

This process ends when all the image data is processed.

As described above, according to the present invention, in the conventional hardware processing method, only the length and location of information generated on the current line can be obtained, whereas in the present invention, the relationship between generated information and other neighboring information is obtained. It is possible to grasp, and there is an advantage that can significantly reduce the processing time compared to the conventional method of processing with software.

Claims (1)

Two line buffers (1, 2) using SRAM, a D flip-flop (3) for the switching switch of the line buffers (1, 2), a bit address counter (4) and a line address counter of binary image data ( 5), a 2 × 2 window D flip-flop array 6, a PROM 7 storing a pattern of reference information, an address code recording address counter 8, and extracted information code recording. An image encoding apparatus using a line buffer, comprising: an SRAM (9).

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