KR900008370B1 - Digital color signal decoding circuit - Google Patents

Digital color signal decoding circuit Download PDF

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KR900008370B1
KR900008370B1 KR1019870013671A KR870013671A KR900008370B1 KR 900008370 B1 KR900008370 B1 KR 900008370B1 KR 1019870013671 A KR1019870013671 A KR 1019870013671A KR 870013671 A KR870013671 A KR 870013671A KR 900008370 B1 KR900008370 B1 KR 900008370B1
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signal
digital
color
composite video
signals
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KR1019870013671A
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KR890009205A (en
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인웅식
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주식회사 금성사
최근선
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/66—Circuits for processing colour signals for synchronous demodulators

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  • Processing Of Color Television Signals (AREA)

Abstract

A decoding circuit for digitally processing a composite video signal comprises an A/D converter (14), a digital filter (18) for dividing a digital composite video signal into a luminance signal and chrominance signals, a sync. detecter (15) for detecting a sync. signal from the composite video signal, a PLL circuit (16) for locking a clock signal of a sampling clock generator (17) and a sync. signal of a ROM (19) with a detected sync. signal, multipliers (20,21), digital filters (22,23) for eliminating the harmonic signal from the outputs of multipliers, and a matrix circuit (24) for providing R, G, B colour signals using luminance signal and the outputs of digital filters (22,23).

Description

디지탈 색신호 디코딩회로Digital Color Signal Decoding Circuit

제1도는 일반적인 TV의 구성도.1 is a block diagram of a general TV.

제2도는 종래 TV의 색신호 디모듈레이터 회로도.2 is a color signal demodulator circuit diagram of a conventional TV.

제3도는 본 발명에 따른 TV의 색신호 디모듈레이터 회로도.3 is a color signal demodulator circuit diagram of a TV according to the present invention;

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

6 : 색신호 디모듈레이터 14 : A/D변환기6: color signal demodulator 14: A / D converter

15 : 동기 검출기 16 : PLL15: sync detector 16: PLL

17 : 샘플링 클럭발생기 18,22,23 : 디지탈 필터17: sampling clock generator 18, 22, 23: digital filter

19 : 롬 20,21 : 곱셈기19: Romans 20,21: Multipliers

24 : 매트릭스 회로24: matrix circuit

본 발명은 디지탈 TV의 색합성신호의 디지탈 디모듈레이터(Demodulator)에 관한것으로 특히 아날로그방식의 색신호(R,G,B)검출을 디지탈 방식으로 검출하도록 하여 디지탈 TV에 적당하도록 구성한 디지탈색신호 디코딩(Decoding)회로에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator (demodulator) of color synthesis signals of a digital TV. In particular, an analog color signal (R, G, B) detection is performed by a digital method. It's about the circuit.

일반적으로 TV의 시스템 구성은 제1도에서 보는 바와 같이 TV 수신안테나(1)가 튜너(2)를 거쳐 비데오 IF단(3)에 연결되며, 비데오 IF단(3)은 음성 IF 디모듈레이터(4)를 거쳐 스피커(5)에 연결되며 또한 색신호 디모듈레이터(6)와 플라이백 트랜스(8)를 각각 거쳐 브라운관(7)에 접속되는 구성으로 되어 있는데, 여기서 종래의 색신호 디모듈레이터(6)의 구성은 제2도에서 보는 바와 같이 아날로그 필터(9), 1H지연부(10), 가산기(11), 감산기(12), 매트릭스회로(13)로 구성되었다.In general, the system configuration of a TV is as shown in Figure 1, the TV receiving antenna (1) is connected to the video IF stage (3) via a tuner (2), the video IF stage (3) is a voice IF demodulator (4) It is connected to the speaker (5) via the color signal demodulator (6) and flyback transformer (8), respectively, is configured to be connected to the tube (7), where the conventional color signal demodulator (6) has a configuration As shown in the figure, an analog filter 9, a 1H delay unit 10, an adder 11, a subtractor 12, and a matrix circuit 13 were formed.

상기 회로구성의 동작상태를 살펴보면, 비데오 IF단(3)으로부터 출력되는 콤포지트(Composite) 비데오신호(가)는 색신호 디모듈레이터(6)의 아날로그 필터(9)를 거쳐 휘도신호(Y)와 색합성신호(R-Y,B-Y)로 분리되고, 휘도신호(Y)는 매트릭스회로(13)에 인가되며, 색합성신호(R-Y,B-Y)는 1H지연부(10)와 가산기(11) 및 감산기(12)로 각각 인가되는데, 여기서 색신호를 분리하기 위해 U=R-Y, V=B-Y라하면 신호는 (U+V) 또는 (U-V)로 합성되어 있으므로 이 신호는 1H지연부(10)에서 첫번째 라인이 지연된 후 가산기(11)에서 가산되어 2U가 출력되며, 감산기(12)에서 감산되면 2V가 출력되어 색합성신호는 R-Y신호와 B-Y신호로 분리되어 매트릭스회로(13)에 인가되게 된다.Referring to the operation state of the circuit configuration, the composite video signal (A) output from the video IF stage 3 passes through the luminance signal (Y) and the color synthesis signal through the analog filter (9) of the color signal demodulator (6). (RY, BY), the luminance signal (Y) is applied to the matrix circuit 13, and the color synthesis signal (RY, BY) to the 1H delay unit (10), the adder (11) and the subtractor (12). If U = RY, V = BY to separate the color signal, the signal is synthesized as (U + V) or (UV), so this signal is added after the first line is delayed in the 1H delay section 10. 2U is added and subtracted by subtractor 12, and 2V is outputted by subtracter 12 so that the color synthesis signal is separated into an RY signal and a BY signal and applied to the matrix circuit 13.

그러므로 매트릭스회로(13)는 인가된 휘도신호(Y)와, 색합성신호(R-Y,B-Y)를 조합하여 출력단으로 색신호(R,G,B)를 출력(나)시키게 된다.Therefore, the matrix circuit 13 outputs the color signals R, G, and B to the output terminal by combining the applied luminance signal Y and the color combining signals R-Y, B-Y.

상기와 같은 기술은 아날로그 방식의 색신호 디모듈레이터로서 신호를 처리하도록 되어 있으므로 디지탈 TV의 색신호 처리에 적용이 불가능하게 되었다.Since the above-described technology processes signals as analog color signal demodulators, it cannot be applied to color signal processing of digital TVs.

이에 본 발명은 상기한 문제점을 개선시키기 위해 안출된 것으로서, 간단한 회로를 구성시켜 색신호검출을 디지탈 방식으로 검출하도록 하여 디지탈 TV에 사용이 가능하도록 한것으로, 이하 그의 기술구성을 첨부된 도면에 따라 설명하면 다음과 같다.Accordingly, the present invention has been made to improve the above problems, and by configuring a simple circuit to detect the color signal detection in a digital manner to be used in digital TV, the following description of the technical configuration according to the accompanying drawings As follows.

제3도는 본 발명에 따른 색신호 디모듈레이터 회로를 나타낸 것으로 그의 연결구성을 살펴보면, 제1도의 비데오 IF단(3)으로부터 출력되는 콤포지트 비데오 신호(가)는 A/D변환기(14)와 동기 검출기(15) 및 PLL(Phase Locked Loop)부(16)를 순차거쳐 롬(Rom)(19)에 인가되도록 구성하고, 샘플링 클럭발생기(17)는 일측으로 A/D변환기(14)와 연결되며 타 일측으로는 PLL부(I6)와 상호연결되고, 상기 A/D변환기(14)에 연결된 디지탈 필터(18)는 디지탈로 변환된 비데오 신호를 휘도신호(Y)와 색합성신호 R-Y,B-Y로 분리하여 휘도신호(Y)는 매트릭스회로(24)에 인가하고, 색합성신호 R-Y,B-Y는 곱셈기(20)(21)에 각각 인가되도록 구성하고, 또한 PLL(16)에 연결된 롬(19)으로부터 신호(f)(g)를 인가받는 상기 곱셈기(20)(21)의 출력은 디지탈 필터(22)(23)를 각각 거쳐 매트릭스회로(24)에 인가되도록한 구성으로, 상기 회로구성의 동작상태 및 작용효과를 첨부된 도면에 따라 설명하면 다음과 같다.3 shows a color signal demodulator circuit according to the present invention. Looking at the connection configuration thereof, the composite video signal outputted from the video IF stage 3 of FIG. 1 is an A / D converter 14 and a synchronization detector 15. ) And PLL (Phase Locked Loop) 16 are sequentially applied to the ROM 19, and the sampling clock generator 17 is connected to the A / D converter 14 on one side and to the other side. Is connected to the PLL unit I6, and the digital filter 18 connected to the A / D converter 14 separates the digitally converted video signal into the luminance signal Y and the color synthesis signals RY and BY to obtain luminance. The signal Y is applied to the matrix circuit 24, and the color synthesis signals RY and BY are configured to be applied to the multipliers 20 and 21, respectively, and the signal f from the ROM 19 connected to the PLL 16 is also applied. The outputs of the multipliers 20 and 21 to which g is applied are applied to the matrix circuit 24 via the digital filters 22 and 23, respectively. In the configuration, the operation state and the effect of the circuit configuration will be described with reference to the accompanying drawings.

제3도에서 비데오 IF단(3)으로부터 출력되는 콤포지트 비데오 신호(가)는 연속적인 아날로그 신호이므로 이 신호는 A/D변환기(14)를 거쳐 불연속적인 디지탈 콤포지트 비데오 신호(a)로 변환되어 출력된다.In FIG. 3, since the composite video signal (a) output from the video IF stage 3 is a continuous analog signal, this signal is converted into a discontinuous digital composite video signal (a) via the A / D converter 14 and output. do.

즉 콤포지트 비데오 신호(가)를 샘플링 클럭발생기(17)에서 발생되는 샘플링 클럭신호(d)로 샘플링하여 디지탈 신호로 만들고, 이를 다시 소스 코딩(Source Coding)하여 디지탈 데이타(7비트∼8비트로서 진폭을 표시하는 신호)로 만들어 디지탈 필터(18)에 인가시킨다.That is, the composite video signal (A) is sampled into a sampling clock signal (d) generated by the sampling clock generator 17 to be a digital signal, and source coded again to digital data (amplitude as 7 to 8 bits, amplitude). Is applied to the digital filter 18.

한편 콤포지트 비데오 신호(가)중 동기부분은 동기 검출기(15)로 인가되어 동기신호를 검출하여 PLL(16)에 인가시킨다.On the other hand, the synchronous part of the composite video signal (a) is applied to the synchronous detector 15 to detect and apply the synchronous signal to the PLL 16.

또한 PLL(16)은 샘플링 클럭발생기(17)의 클럭신호(b)와 피이드백 루프(c)를 통해 클럭을 로크(Lock)시키며 동시에 롬(19)으로 인가되는 신호(e)도 로크시키게 된다.In addition, the PLL 16 locks the clock through the clock signal b and the feedback loop c of the sampling clock generator 17, and simultaneously locks the signal e applied to the ROM 19. .

한편 상기 A/D변환기(14)에서 변환된 디지탈 신호(a)는 상기 디지탈 필터(18)를 거쳐 불연속적인 휘도신호(Y)와 색신호(R-Y,B-Y)로 출력되어 휘도신호(Y)는 매트릭스회로(24)에 인가되며 색신호(R-Y,B-Y)는 곱셈기(20)(21)에 각각 인가되게 되는데, U=R-Y, V=B-Y라 놓으면 디지탈 필터(18)에서 출력되는 색신호(R-Y,B-Y)는 U Sin Wc△t±Vcos Wc△t의 신호 성분이며, 이 신호는 롬(19)으로부터 출력되는 신호 f=2 Sin Wc△t, g=±2 Cos Wc△t와 곱셈기(20)(21)에서 곱셈하게 된다.On the other hand, the digital signal a converted by the A / D converter 14 is output as a discrete luminance signal Y and a color signal RY and BY through the digital filter 18, so that the luminance signal Y is matrixed. The color signals RY and BY are applied to the circuit 24, and the color signals RY and BY are respectively applied to the multipliers 20 and 21. When U = RY and V = BY, the color signals RY and BY outputted from the digital filter 18 are applied. Is a signal component of U Sin WcΔt ± Vcos WcΔt, which is a signal f = 2 Sin WcΔt, g = ± 2 Cos WcΔt and a multiplier 20 (21) output from the ROM 19. ) To multiply.

상기에 따라 곱셈기(20)(21)의 각 출력단(h)(i)으로는According to the above, each output terminal h (i) of the multipliers 20 and 21 is

h=U-U×Cos2 Wc△t±V ×Sin Wc△t와h = U-U x Cos2 WcΔt ± V x Sin WcΔt and

i=V+V×Cos2 Wc△t±U×Sin2 Wc△t의 신호성분이 출력되고 디지탈 필터(22)(23)에 각각 인가되어 고조파 신호가 제거된다.Signal components i = V + V x Cos2 Wc? t + U x Sin2 Wc? t are output and applied to the digital filters 22 and 23, respectively, to remove harmonic signals.

그러므로 디지탈 필터(22)(23)를 거쳐 출력된 신호는 U와 V로 되어 순수한 R-Y신호와 B-Y신호와 B-Y신호로 매트릭스회로(24)에 인가되고, 매트릭스회로(24)에서는 Y+R-Y=R, Y+R-Y=B, 그리고(R-Y)와 (B-Y)를 조합하여 G-Y를 만들고 Y+G-Y=G로 하여 색신호(R,G,B)를 출력시키게 된다.Therefore, the signals output through the digital filters 22 and 23 become U and V, and are applied to the matrix circuit 24 as pure RY signals, BY signals, and BY signals, and Y + RY = R in the matrix circuits 24. , Y + RY = B, and (RY) and (BY) are combined to make GY, and Y + GY = G to output the color signals (R, G, B).

따라서 본 발명에 따른 디지탈 색신호 디코딩회로는 이상의 설명에서와 같이 간단한 회로의 구성으로 색신호검출을 디지탈 방식으로 검출하도록 하므로서 디지탈 TV에 적용이 가능하게 되는 효과를 갖게된다.Therefore, the digital color signal decoding circuit according to the present invention has an effect that can be applied to digital TV by detecting the color signal detection in a digital manner with a simple circuit configuration as described above.

Claims (2)

콤포지트 비데오 신호를 디지탈 신호처리하는 디코딩회로에 있어서, 샘플링 클럭신호에 의해 콤포지트 비데오 신호(가)를 디지탈 콤프지트 비데오 신호(a)로 변환하는 A/D변환기(14)와, 상기 A/D변환기(14)에서 출력되는 디지탈 콤포지트 비데오 신호(a)를 인가받아 휘도신호(Y)와 색신호(R-Y,B-Y)로 분리 출력하는 디지탈 필터(18)와, 콤포지트 비데오 신호(가)에서 동기신호를 검출하는 동기 검출기(15)와, 상기 동기 검출기(15)에서 검출된 동기신호를 인가받아 샘플링 클럭발생기(17)의 클럭신호(b)와 피이드백 루프(c)를 통해 클럭을 로크시키며 동시에 롬(19)으로 인가되는 동기신호(e)도 로크시키는 PLL(16)과, 상기 PLL(16)에서 출력되는 동기신호(e)를 인가받아 신호(f,g)를 출력하는 롬(19)과, 상기 롬(19)의 출력신호(f)(g)와 디지탈 필터(18)에서 분리된 색신호(R-Y)(B-Y)를 곱하는 곱셈기(20)(21)와, 상기 곱셈기(20)(21)의 출력신호(h)(1)에서 고조파 신호를 제거하는 디지탈 필터(22)(23)와, 상기 디지탈 필터(22)(23)에서 출력되는 신호(R-Y)(B-Y)와 디지탈 필터(18)에서 분리된 휘도신호(Y)를 인가받아 색신호(R,G,B)를 출력시키는 매트릭스회로(24)를 포함하여 구성된 것을 특징으로 하는 디지탈 색신호의 디코딩회로.A decoding circuit for digitally processing a composite video signal, comprising: an A / D converter (14) for converting a composite video signal (a) into a digital composite video signal (a) by a sampling clock signal, and the A / D converter A digital filter 18, which receives the digital composite video signal a output from (14) and separately outputs the luminance signal Y and the color signals RY and BY, and detects a synchronization signal from the composite video signal A. The synchronization detector 15 and the synchronization signal detected by the synchronization detector 15 are applied to lock the clock through the clock signal b and the feedback loop c of the sampling clock generator 17, and simultaneously A PLL 16 for locking the synchronization signal e applied to the signal 19), a ROM 19 for receiving the synchronization signal e outputted from the PLL 16 and outputting signals f and g, The output signal f (g) of the ROM 19 and the color signal RY (BY) separated from the digital filter 18 are A multiplier (20) and a multiplier (20) and a digital filter (22) and a digital filter (22) to remove harmonic signals from the output signals (h) (1) of the multipliers (20) and (21). And a matrix circuit 24 for receiving the signal RY (BY) output from 23 and the luminance signal Y separated from the digital filter 18 and outputting the color signals R, G, and B. A digital color signal decoding circuit. 제1항에 있어서, 롬(19)의 출력신호(f)(g)는 f=2 Sin Wc△t, b=±2Cos Wc△t로 함을 특징으로 하는 디지탈 색신호 디코딩회로.The digital color signal decoding circuit according to claim 1, wherein the output signal f (g) of the ROM (19) is f = 2 Sin WcΔt and b = ± 2Cos WcΔt.
KR1019870013671A 1987-11-30 1987-11-30 Digital color signal decoding circuit KR900008370B1 (en)

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KR1019870013671A KR900008370B1 (en) 1987-11-30 1987-11-30 Digital color signal decoding circuit

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KR890009205A KR890009205A (en) 1989-07-13
KR900008370B1 true KR900008370B1 (en) 1990-11-17

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KR1019870013671A KR900008370B1 (en) 1987-11-30 1987-11-30 Digital color signal decoding circuit

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Publication number Priority date Publication date Assignee Title
KR100480569B1 (en) * 1997-11-12 2005-09-29 삼성전자주식회사 Video decoder having multi-function

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