KR900007194U - 전가산기회로 - Google Patents

전가산기회로

Info

Publication number
KR900007194U
KR900007194U KR2019880015353U KR880015353U KR900007194U KR 900007194 U KR900007194 U KR 900007194U KR 2019880015353 U KR2019880015353 U KR 2019880015353U KR 880015353 U KR880015353 U KR 880015353U KR 900007194 U KR900007194 U KR 900007194U
Authority
KR
South Korea
Prior art keywords
adder circuit
full adder
full
circuit
adder
Prior art date
Application number
KR2019880015353U
Other languages
English (en)
Other versions
KR920008353Y1 (ko
Inventor
최영철
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019880015353U priority Critical patent/KR920008353Y1/ko
Publication of KR900007194U publication Critical patent/KR900007194U/ko
Application granted granted Critical
Publication of KR920008353Y1 publication Critical patent/KR920008353Y1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
KR2019880015353U 1988-09-19 1988-09-19 전가산기회로 KR920008353Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019880015353U KR920008353Y1 (ko) 1988-09-19 1988-09-19 전가산기회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019880015353U KR920008353Y1 (ko) 1988-09-19 1988-09-19 전가산기회로

Publications (2)

Publication Number Publication Date
KR900007194U true KR900007194U (ko) 1990-04-03
KR920008353Y1 KR920008353Y1 (ko) 1992-11-20

Family

ID=19279478

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019880015353U KR920008353Y1 (ko) 1988-09-19 1988-09-19 전가산기회로

Country Status (1)

Country Link
KR (1) KR920008353Y1 (ko)

Also Published As

Publication number Publication date
KR920008353Y1 (ko) 1992-11-20

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20021018

Year of fee payment: 11

EXPY Expiration of term